Patents by Inventor SHIGEFUMI DOHI
SHIGEFUMI DOHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10109660Abstract: A laminated semiconductor device includes: a first semiconductor element provided with a photoelectric conversion region on its main surface; an extended portion extended outwardly from a side end surface of the first semiconductor element; a redistribution layer formed on a first surface of the extended portion; a second semiconductor element provided on the main surface of the first semiconductor element so as to extend to the extended portion from an outside of the photoelectric conversion region, the second semiconductor element being electrically connected to the first semiconductor element and the redistribution layer; and a first electrode pad formed on the redistribution layer and electrically connected to the second semiconductor element via the redistribution layer.Type: GrantFiled: July 23, 2015Date of Patent: October 23, 2018Assignee: PANASONIC CORPORATIONInventors: Shigefumi Dohi, Toshitaka Akahoshi
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Patent number: 9589877Abstract: A semiconductor device includes an expanded semiconductor chip having a first semiconductor chip and an expanded portion extending outward from a side surface of the first semiconductor chip, a second semiconductor chip provided so as to be connected to the expanded semiconductor chip via a plurality of first bumps, and a base provided so as to be connected to the expanded semiconductor chip via a plurality of second bumps. The first bumps are provided between the first semiconductor chip and the second semiconductor chip. The second bumps are provided between the expanded portion and the base.Type: GrantFiled: January 8, 2014Date of Patent: March 7, 2017Assignee: Panasonic CorporationInventors: Shigefumi Dohi, Kiyomi Hagihara
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Patent number: 9502455Abstract: A downsized, highly reliable optical apparatus is stably and easily manufactured with high productivity. The optical apparatus includes: an optical device having a principal surface including an optical unit; a transparent member disposed facing the optical unit; a semiconductor device disposed above a back surface of the optical device and electrically connected to the optical device, the back surface being opposite the principal surface; and a resin member provided in a region adjacent to the optical device and the semiconductor device above a surface of the transparent member, the surface of the transparent member facing the optical device.Type: GrantFiled: May 26, 2015Date of Patent: November 22, 2016Assignee: PANASONIC CORPORATIONInventors: Toshitaka Akahoshi, Hiroki Yamashita, Shigefumi Dohi
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Publication number: 20160336366Abstract: A light-receiving device which has high reliability and high sensitivity is provided with low cost. The device has a laminate type device structure in which a photoelectric converter and a scanning circuit unit are connected by microbumps, and a structure in which a transparent conductive film is formed on a photodiode of a photoelectric converter. A rewiring is formed so as to have a function of an OB region, and an electrode for supplying a voltage to a scanning circuit and the photodiode on the transparent conductive film, and the rewiring is electrically connected to an external electrode by a wire.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventor: SHIGEFUMI DOHI
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Patent number: 9337172Abstract: Provided is a small and thin semiconductor device while preventing contamination of a wire bonding terminal caused by creeping-up of a die bond. The semiconductor device includes: a first semiconductor chip having a main surface formed with electrodes; an extension part extended outward from a side end surface of the first semiconductor chip; a rewiring layer formed from the main surface of the first semiconductor chip to a first surface of the extension part; a connection terminal provided on the rewiring layer of the extension part; a die bond that fixes the first semiconductor chip and the extension part to a substrate; and in the extension part, a step outside the connection terminal.Type: GrantFiled: August 10, 2015Date of Patent: May 10, 2016Assignee: PANASONIC CORPORATIONInventor: Shigefumi Dohi
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Patent number: 9240391Abstract: A semiconductor device includes: a first semiconductor chip; a second semiconductor chip placed such that a front face of the second semiconductor chip faces a front face of the first semiconductor chip, and being smaller in size than the first semiconductor chip; an expansion portion extending outward from at least one side face of the second semiconductor chip; a wiring board placed such that a front face of the wiring board faces the front face of the first semiconductor chip and a back face of the second semiconductor chip; and a first interconnect formed on the back face of the second semiconductor chip and a back face of the expansion portion, and being in connection to the wiring board.Type: GrantFiled: December 26, 2013Date of Patent: January 19, 2016Assignee: Panasonic CorporationInventors: Noriyuki Nagai, Shigefumi Dohi
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Publication number: 20150348946Abstract: Provided is a small and thin semiconductor device while preventing contamination of a wire bonding terminal caused by creeping-up of a die bond. The semiconductor device includes: a first semiconductor chip having a main surface formed with electrodes; an extension part extended outward from a side end surface of the first semiconductor chip; a rewiring layer formed from the main surface of the first semiconductor chip to a first surface of the extension part; a connection terminal provided on the rewiring layer of the extension part; a die bond that fixes the first semiconductor chip and the extension part to a substrate; and in the extension part, a step outside the connection terminal.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventor: SHIGEFUMI DOHI
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Publication number: 20150333096Abstract: A laminated semiconductor device includes: a first semiconductor element provided with a photoelectric conversion region on its main surface; an extended portion extended outwardly from a side end surface of the first semiconductor element; a redistribution layer formed on a first surface of the extended portion; a second semiconductor element provided on the main surface of the first semiconductor element so as to extend to the extended portion from an outside of the photoelectric conversion region, the second semiconductor element being electrically connected to the first semiconductor element and the redistribution layer; and a first electrode pad formed on the redistribution layer and electrically connected to the second semiconductor element via the redistribution layer.Type: ApplicationFiled: July 23, 2015Publication date: November 19, 2015Inventors: SHIGEFUMI DOHI, TOSHITAKA AKAHOSHI
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Publication number: 20150255500Abstract: A downsized, highly reliable optical apparatus is stably and easily manufactured with high productivity. The optical apparatus includes: an optical device having a principal surface including an optical unit; a transparent member disposed facing the optical unit; a semiconductor device disposed above a back surface of the optical device and electrically connected to the optical device, the back surface being opposite the principal surface; and a resin member provided in a region adjacent to the optical device and the semiconductor device above a surface of the transparent member, the surface of the transparent member facing the optical device.Type: ApplicationFiled: May 26, 2015Publication date: September 10, 2015Inventors: TOSHITAKA AKAHOSHI, HIROKI YAMASHITA, SHIGEFUMI DOHI
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Publication number: 20140117542Abstract: A semiconductor device includes an expanded semiconductor chip having a first semiconductor chip and an expanded portion extending outward from a side surface of the first semiconductor chip, a second semiconductor chip provided so as to be connected to the expanded semiconductor chip via a plurality of first bumps, and a base provided so as to be connected to the expanded semiconductor chip via a plurality of second bumps. The first bumps are provided between the first semiconductor chip and the second semiconductor chip. The second bumps are provided between the expanded portion and the base.Type: ApplicationFiled: January 8, 2014Publication date: May 1, 2014Applicant: Panasonic CorporationInventors: SHIGEFUMI DOHI, KIYOMI HAGIHARA
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Publication number: 20140103543Abstract: A semiconductor device includes: a first semiconductor chip; a second semiconductor chip placed such that a front face of the second semiconductor chip faces a front face of the first semiconductor chip, and being smaller in size than the first semiconductor chip; an expansion portion extending outward from at least one side face of the second semiconductor chip; a wiring board placed such that a front face of the wiring board faces the front face of the first semiconductor chip and a back face of the second semiconductor chip; and a first interconnect formed on the back face of the second semiconductor chip and a back face of the expansion portion, and being in connection to the wiring board.Type: ApplicationFiled: December 26, 2013Publication date: April 17, 2014Applicant: Panasonic CorporationInventors: NORIYUKI NAGAI, SHIGEFUMI DOHI
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Patent number: 8698309Abstract: A semiconductor device includes a first semiconductor device and second semiconductor device stacked on the first semiconductor device. The first semiconductor device includes a first interconnect substrate, a first semiconductor element provided on an upper surface of the first interconnect substrate, a first electrode provided on the upper surface of the first interconnect substrate, and an insulating layer having an opening portion through which part of the first electrode is exposed. The second semiconductor device includes a second interconnect substrate, a second semiconductor element provided on an upper surface of the second interconnect substrate, a second electrode provided on a lower surface of the second interconnect substrate, and an inter-device connection terminal connected to the second electrode. Part of the first electrode exposed through the opening portion has a smaller area than an area of the opening portion.Type: GrantFiled: February 16, 2012Date of Patent: April 15, 2014Assignee: Panasonic CorporationInventors: Shigefumi Dohi, Kouji Oomori
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Publication number: 20120146244Abstract: A semiconductor device includes a first semiconductor device and second semiconductor device stacked on the first semiconductor device. The first semiconductor device includes a first interconnect substrate, a first semiconductor element provided on an upper surface of the first interconnect substrate, a first electrode provided on the upper surface of the first interconnect substrate, and an insulating layer having an opening portion through which part of the first electrode is exposed. The second semiconductor device includes a second interconnect substrate, a second semiconductor element provided on an upper surface of the second interconnect substrate, a second electrode provided on a lower surface of the second interconnect substrate, and an inter-device connection terminal connected to the second electrode. Part of the first electrode exposed through the opening portion has a smaller area than an area of the opening portion.Type: ApplicationFiled: February 16, 2012Publication date: June 14, 2012Applicant: PANASONIC CORPORATIONInventors: SHIGEFUMI DOHI, KOUJI OOMORI