Patents by Inventor Shigeharu Monoe
Shigeharu Monoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9147831Abstract: A method for fabricating a crystal unit, including a preparing step, a bonding step, and a separating step, is provided. The preparing step prepares a quartz plate and a supporting substrate with a recess that is larger than the vibrating region on a surface of the supporting substrate. The recess corresponds to a vibrating region in the crystal unit. The bonding step bonds the quartz plate to the surface of the supporting substrate such that the quartz plate is separated from the supporting substrate in the recess. The separating step separates the quartz plate into the vibrating region and the framing portion by performing dry etching on the quartz plate such that the quartz plate has a shape that connects the vibrating region to the framing portion via a supporting beam. The framing portion surrounds the vibrating region.Type: GrantFiled: September 28, 2012Date of Patent: September 29, 2015Assignee: NIHON DEMPA KOGYO CO., LTD.Inventors: Tomotaka Kuroda, Makoto Hatano, Shigeharu Monoe
-
Patent number: 8669663Abstract: A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed.Type: GrantFiled: July 21, 2011Date of Patent: March 11, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinya Sasagawa, Satoru Okamoto, Shigeharu Monoe
-
Patent number: 8232556Abstract: An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and an impurity region, which is provided over a substrate, a first conductive film provided over the channel formation region with a gate insulating film interposed therebetween, a first interlayer insulating film provided to cover the first conductive film, a second conductive film provided over the first interlayer insulating film so as to overlap with at least part of the impurity region, a second interlayer insulating film provided over the second conductive film, and a third conductive film provided over the second interlayer insulating film so as to be electrically connected to the impurity region through an opening.Type: GrantFiled: May 3, 2011Date of Patent: July 31, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Ryo Arasawa, Aya Miyazaki, Shigeharu Monoe, Shunpei Yamazaki
-
Patent number: 8143168Abstract: The present invention discloses technique of etching selectively a layer containing siloxane. The present invention provides a semiconductor device with reduced operation deterioration due to etching failure. A method for manufacturing a semiconductor device comprises steps of forming a conductive layer electrically connecting to a transistor, an insulating layer covering the conductive layer, and a mask formed over the insulating layer; and etching the insulating layer with a processing gas including a hydrogen bromide gas.Type: GrantFiled: January 11, 2011Date of Patent: March 27, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinya Sasagawa, Shigeharu Monoe
-
Publication number: 20110272816Abstract: A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed.Type: ApplicationFiled: July 21, 2011Publication date: November 10, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shinya SASAGAWA, Satoru OKAMOTO, Shigeharu MONOE
-
Patent number: 8043902Abstract: The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode.Type: GrantFiled: July 30, 2009Date of Patent: October 25, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Shigeharu Monoe, Shunpei Yamazaki
-
Publication number: 20110204424Abstract: An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and an impurity region, which is provided over a substrate, a first conductive film provided over the channel formation region with a gate insulating film interposed therebetween, a first interlayer insulating film provided to cover the first conductive film, a second conductive film provided over the first interlayer insulating film so as to overlap with at least part of the impurity region, a second interlayer insulating film provided over the second conductive film, and a third conductive film provided over the second interlayer insulating film so as to be electrically connected to the impurity region through an opening.Type: ApplicationFiled: May 3, 2011Publication date: August 25, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Ryo ARASAWA, Aya MIYAZAKI, Shigeharu MONOE, Shunpei YAMAZAKI
-
Patent number: 7989351Abstract: A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed.Type: GrantFiled: April 28, 2009Date of Patent: August 2, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinya Sasagawa, Satoru Okamoto, Shigeharu Monoe
-
Patent number: 7952100Abstract: An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and an impurity region, which is provided over a substrate, a first conductive film provided over the channel formation region with a gate insulating film interposed therebetween, a first interlayer insulating film provided to cover the first conductive film, a second conductive film provided over the first interlayer insulating film so as to overlap with at least part of the impurity region, a second interlayer insulating film provided over the second conductive film, and a third conductive film provided over the second interlayer insulating film so as to be electrically connected to the impurity region through an opening.Type: GrantFiled: September 14, 2007Date of Patent: May 31, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Ryo Arasawa, Aya Miyazaki, Shigeharu Monoe, Shunpei Yamazaki
-
Publication number: 20110104892Abstract: The present invention discloses technique of etching selectively a layer containing siloxane. The present invention provides a semiconductor device with reduced operation deterioration due to etching failure. A method for manufacturing a semiconductor device comprises steps of forming a conductive layer electrically connecting to a transistor, an insulating layer covering the conductive layer, and a mask formed over the insulating layer; and etching the insulating layer with a processing gas including a hydrogen bromide gas.Type: ApplicationFiled: January 11, 2011Publication date: May 5, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shinya SASAGAWA, Shigeharu MONOE
-
Patent number: 7875506Abstract: The present invention discloses technique of etching selectively a layer containing siloxane. The present invention provides a semiconductor device with reduced operation deterioration due to etching failure. A method for manufacturing a semiconductor device comprises steps of forming a conductive layer electrically connecting to a transistor, an insulating layer covering the conductive layer, and a mask formed over the insulating layer; and etching the insulating layer with a processing gas including a hydrogen bromide gas.Type: GrantFiled: October 7, 2005Date of Patent: January 25, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinya Sasagawa, Shigeharu Monoe
-
Publication number: 20110012113Abstract: To provide a manufacturing method in which LDD regions with different widths are formed in a self-aligned manner, and the respective widths are precisely controlled in accordance with each circuit. By using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function formed of a diffraction grating pattern or a semi-transparent film, the width of a region with a small thickness of a gate electrode can be freely set, and the widths of two LDD regions capable of being formed in a self-aligned manner with the gate electrode as a mask can be different in accordance with each circuit. In one TFT, both of two LDD regions with different widths overlap a gate electrode.Type: ApplicationFiled: September 23, 2010Publication date: January 20, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto Ohnuma, Shigeharu Monoe
-
Patent number: 7807516Abstract: To provide a manufacturing method in which LDD regions with different widths are formed in a self-aligned manner, and the respective widths are precisely controlled in accordance with each circuit. By using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function formed of a diffraction grating pattern or a semi-transparent film, the width of a region with a small thickness of a gate electrode can be freely set, and the widths of two LDD regions capable of being formed in a self-aligned manner with the gate electrode as a mask can be different in accordance with each circuit. In one TFT, both of two LDD regions with different widths overlap a gate electrode.Type: GrantFiled: June 21, 2006Date of Patent: October 5, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Shigeharu Monoe
-
Publication number: 20100015764Abstract: The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode.Type: ApplicationFiled: July 30, 2009Publication date: January 21, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto Ohnuma, Shigeharu Monoe, Shunpei Yamazaki
-
Patent number: 7588970Abstract: The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode.Type: GrantFiled: June 2, 2006Date of Patent: September 15, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Shigeharu Monoe, Shunpei Yamazaki
-
Patent number: 7579270Abstract: It is an object of the present invention to provide a method for manufacturing a highly reliable semiconductor device with preferable yield. In the invention, two-step etching is performed when selectively removing an interlayer insulating film with at least two layers constituting a semiconductor device, and forming an opening. One feature of the invention is that at least either one of a first gas (a first etching gas) and a second gas (a second etching gas) used at the time of the two-step etching is added with an inert gas.Type: GrantFiled: November 17, 2006Date of Patent: August 25, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomohiko Sato, Shigeharu Monoe, Shinya Sasagawa
-
Publication number: 20090206494Abstract: A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed.Type: ApplicationFiled: April 28, 2009Publication date: August 20, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shinya SASAGAWA, Satoru OKAMOTO, Shigeharu MONOE
-
Patent number: 7563658Abstract: The present invention relates to a method for manufacturing a semiconductor film, including the steps of forming a transparent conductive film, forming a first conductive film over the transparent conductive film, forming a second conductive film over the first conductive film, etching the second conductive film with a gas including chlorine, and etching the first conductive film with a gas including fluorine. During etching of the second conductive film with a gas including chlorine, the transparent conductive film is protected by the first conductive film. During etching of the first conductive film with the gas including fluorine, the transparent conductive film does not react with the gas including fluorine. Therefore, no particle is formed.Type: GrantFiled: December 22, 2005Date of Patent: July 21, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihiro Ishizuka, Satoru Okamoto, Shigeharu Monoe, Shunpei Yamazaki
-
Patent number: 7560315Abstract: It is an object of the present invention to enhance a selection ratio in an etching process, and provide a method for manufacturing a semiconductor device that has favorable uniform characteristics with high yield. In a method for manufacturing a semiconductor device according to the present invention, a first layer is formed over a substrate, second layer is formed on the first layer, the first layer and the second layer are etched to form a first pattern, and the second layer in the first pattern is selectively etched with plasma of boron trichloride, chlorine, and oxygen using ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) to form a second pattern.Type: GrantFiled: May 23, 2006Date of Patent: July 14, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shigeharu Monoe, Takashi Yokoshima, Shinya Sasagawa
-
Patent number: 7554128Abstract: A light-emitting device, which has a structure that improves an opening ratio and light extraction efficiency, can solve a problem of an etching residue occurred during forming the device itself, and reduce deterioration due to poor coverage and short-circuiting to improve greatly the reliability, and a method for manufacturing the light-emitting device. In the light-emitting device having a structure that improves light extraction efficiency, a material used for forming a first electrode is Ti/TiN/Al (or Al—Ti)/Ti (or TiN).Type: GrantFiled: June 28, 2005Date of Patent: June 30, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoru Okamoto, Shigeharu Monoe, Takashi Yokoshima