Patents by Inventor Shigeharu Murata

Shigeharu Murata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hold-type latch circuit with increased margin in the feedback timing and a memory device using same for holding parity check error
    Patent number: 5399912
    Abstract: A hold-type latch circuit which features an increased operation margin. A feedback circuit feeds the data output logic state of a non-inversion data output terminal of the latch circuit back to a data input terminal thereof, to increase a margin in the setup time ts and holding time th in controlling the data holding capability of the latch circuit, thereby to increase the margin of thereof.
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: March 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shigeharu Murata, Takasi Oomori, Masami Usami, Masato Iwabuchi