Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the transmitter are provided in a single IC (Integrated Circuit) chip and are not overlapped with each other in planar view, and the transmitter includes a coil.

Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit.

Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view.

Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view.

Abstract: An exemplary aspect of the present invention is a memory card that includes: a memory that stores data; a driver that modulates the data stored in the memory; a transmitter that transmits the data modulated by the driver to a receiver provided in an external main unit; and an IC chip having the driver and the transmitter formed therein.

Abstract: An exemplary aspect of the present invention is a memory card that includes: a memory that stores data; a driver that modulates the data stored in the memory; a transmitter that transmits the data modulated by the driver to a receiver provided in an external main unit; and an IC chip having the driver and the transmitter formed therein.

Abstract: A semiconductor integrated circuit has a dummy gate electrode layer formed on a semiconductor substrate, with a gate insulation film interposed. On the first layer insulation film formed on the top of the dummy gate electrode layer, the first signal line is arranged, intersecting with the dummy gate electrode material layer substantially at right angles. On the second layer insulation film formed on the first signal line, a power-supply wiring layer is arranged, extending substantially parallel, and is located right above the dummy gate electrode layer. A contact hole is provided, electrically connecting the power-supply layer to the dummy gate electrode layer.

Abstract: The carry-line comprises a plurality of MOSFETs connected in series. MOSFETs precharge each node when they receive precharge signals /PR. In the case of high-order priority designated mode, when input signals are given for turning on MOSFETs located between one end of the high-order bit side of the carry-line, the control circuit discharges the intermediate node separately from the carry-line. In the case of low-order bit priority designated mode, when input signals are given for turning on MOSFETs located between one end of the low-order bit side of the carry-line and the intermediate node, the control circuit discharges the intermediate node separately from the carry-line.

Abstract: A microcomputer with a built-in ROM for a burst transfer method has a ROM divided into blocks, for reading data by being supplied with an address, a first control circuit for supplying the address to the ROM, an adder for adding a specific address value to the address and outputting an added address which is the result of the addition, a comparator for comparing the next supplied address and the added address and outputting the result of the comparison, a second control circuit for supplying a control signal indicating to the first control circuit that a burst transfer will or will not be executed, based on the result of the comparison output by the comparator, and a selector for selecting data output from each block and outputting the data to a bus.

Abstract: A priority encoder-includes an encoder for coding an input consisting of a plurality of bits, selectors, respectively provided for bit input terminals of the encoder, for respectively receiving corresponding ones of a plurality of bits of an operand input, each of the selectors including a switch circuit to be controlled by an operand input bit, a carry line connected in series with the switch circuit and connected in series with all of the selectors, a first precharge circuit, connected to a carry line portion on one end side of the switch circuit, for precharging the carry line at a predetermined timing, a first detector which is controlled by an enable signal for designating upper bit priority and detects whether a potential of a carry line portion on an upper bit side of the switch circuit is at a discharge level, a second detector which is controlled by an enable signal for designating lower bit priority and detects whether a carry line portion on a lower bit side of the switch circuit is at a discharge

Abstract: The same bit lines are used in common to a fixed data cell array and a memory cell array. The output section of the fixed data cell array is connected to an output circuit, just like the output section of the memory cell array. In response to signal CON supplied from a computer, an array selector examines the states of the arrays and performs switching between the state where one of the arrays can be selected and the state where neither of them can be selected. In the case where an externally-programmable memory, such as an EPROM, is employed, a write control circuit operates with respect only to the memory cell array, and prohibits data from being written in the fixed data cell array. The fixed data cell array is pre-programmed as a nonvolatile memory by programming means different from that used for programming the cells of the memory cell array.

Abstract: A bit position encoder comprises a plurality of judging circuits corresponding in number to bits of input data and connected to receive respective bits of the input data in parallel and a signal specifying the processing sequence for making a judgment on the basis of the result of a judgment from an adjacent judging circuit that has made a judgment of whether a corresponding input bit input thereto has a predetermined value and supplying the result of the judgment to an adjacent judging circuit that has not performed judgment processing yet, a circuit responsive to the results of judgments from the judging circuits for pointing out the bit position in the predetermined value appears first in the direction of judgment processing sequence in a binary code, and a circuit connected to receive the input bits for supplying a result of the logical OR of the input bits to the judging circuits.

Abstract: A semiconductor integrated circuit comprises a plurality of bus line means for transferring data, a plurality of bus line driving means, connected to the bus line means and including one or more FETs, for determining a logical level of the bus line means, and a ground potential wire connected to the bus line driving means and arranged parallel to the bus line means.