Abstract: An error correction system for a difference set cyclic (272, 190) code with 190 data bits and 82 test bits in a packet which is transmitted on a vertical blanking interval of a television signal has been improved. The present system comprises a buffer memory for storing an original data which is subject to correction and corrected data, and an error correction circuit having at least a syndrome register, a majority circuit and a data register. The data transfer between the buffer memory and the error correction circuit is effected by wired logic hardware means without using software operation time of a programmed computer so that computer operation time is not wasted merely for error correction.

Abstract: Disclosed is a synchronizer for establishing synchronism between horizontal and vertical sync pulses of a non-interlaced video signal and those of an interlaced video signal, the number of non-interlaced scan lines being smaller by 2n-1 than the interlaced scan lines, where n is an integer equal to or greater than unity. Two variable frequency clocks are generated, one having a higher frequency variable as a function of a phase difference between the horizontal sync pulses of the two video signals and the other having one half the higher frequency. A first period is defined which runs from a non-interlaced horizontal sync of first occurrence in a given field to a horizontal sync of (n-1)th occurrence in the given field and a second period is defined that runs from the non-interlaced horizontal sync of first occurrence in a subsequent field to a horizontal sync of n-th occurrence in the subsequent field.