Patents by Inventor Shigehiko Sasa

Shigehiko Sasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5682046
    Abstract: A heterojunction bipolar transistor has a support substrate, a collector layer formed on the support substrate, a base layer formed on the collector layer containing arsenic as group V element, a first emitter layer formed on the base layer, containing phosphorus as group V element, and having a band gap wider than the base layer, an emitter passivation layer formed on the first emitter layer made of semiconductor having a function of passivating the surface of the first emitter layer, and a base electrode forming an ohmic contact with the base layer. The whole upper surface of the base layer is covered with the first emitter layer and base electrode, the whole upper surface of the first emitter layer is covered with the emitter passivation layer, and the region of the first emitter layer adjacent to the edge of the base electrode is depleted throughout the full depth thereof.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: October 28, 1997
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Takahashi, Hiroshi Yamada, Kazukiyo Joshin, Shigehiko Sasa
  • Patent number: 5406094
    Abstract: A quantum interference effect transistor comprising a semiconductor substrate, an n-type first semiconductor layer, a channel second semiconductor layer, an n-type third semiconductor layer, a gate electrode, a source electrode, a drain electrode, a source region and a drain region, said second semiconductor layer having an electron affinity larger than that of the first and third layers to generate a two dimensional electron gas channel, characterized in that the channel second layer between the source and drain regions consists of lead portions and a middle portion sandwiched with them, and in the middle portion the channel is divided into two channel passages without forming a separation layer in the second layer. The first, second and third layers form a quantum well structure.
    Type: Grant
    Filed: August 19, 1992
    Date of Patent: April 11, 1995
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Arimoto, Shigehiko Sasa, Akira Endoh
  • Patent number: 5130766
    Abstract: A quantum interference type semiconductor device is composed of at least one bifurcated branch conductive channel with a heterojunction in a semiconductor with a band discontinuity that produced a potential well between two semiconductor regions into which a carrier is injected and from which a carrier is drained, at least one gate electrode is arranged at the side of the one bifurcated branch conduction channel, and a kind of filter using a resonance tunneling barrier arranged before or upstream of the semiconductor region into which a carrier is injected. The filter passes a carrier having a certain energy legvel to the channel whereby the level of the carrier traveling in the channel becomes equal to realize a good quantum interference effect.
    Type: Grant
    Filed: August 3, 1989
    Date of Patent: July 14, 1992
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Arimoto, Shunichi Muto, Shigehiko Sasa, Makoto Okada, Naoki Yokoyama
  • Patent number: 4833508
    Abstract: A field effect semiconductor device which utilizes a 2DEG and is composed of a semi-insulating GaAs substrate; an i-type GaAs active layer; a superlattice structure layer which comprises a first i-type AlAs thin layer, a GaAs thin layer doped with an Si atomic plane, and a second i-type AlAs thin layer, these thin layers forming a GaAs quantum well; and n-type AlGaAs layer; and electrodes for source, drain, and gate.
    Type: Grant
    Filed: December 7, 1987
    Date of Patent: May 23, 1989
    Assignee: Fujitsu Limited
    Inventors: Tomonori Ishikawa, Shigehiko Sasa, Satoshi Hiyamizu
  • Patent number: 4593301
    Abstract: In order to make IC comprising high electron mobility semiconductor device, it is necessary to make the carrier in channel layer not to loose its high mobility by thermal treatment in the IC fabrication process. It has been found that the mobility of two dimensional electron gas (2DEG) is lost by scattering of ionized impurity diffused from doped layer into spacer layer which separates the 2DEG in channel layer from the doped layer. So another spacer (second spacer) is inserted between the spacer (first spacer) and the doped layer to prevent the diffusion of impurity. Proposed multilayered structure is as follows. A channel layer made of i-GaAs is formed on a high resistivity GaAs substrate. Upon which a first spacer layer (prior art) of undoped Al.sub.x Ga.sub.1-x As is formed, over which the second spacer layer of i-GaAs is formed, then over which the doped layer of n-Al.sub.x Ga.sub.1-x As is formed. The thickness of the second spacer layer is approximately 20 .ANG.
    Type: Grant
    Filed: March 1, 1985
    Date of Patent: June 3, 1986
    Assignee: Fujitsu Limited
    Inventors: Tsuguo Inata, Shigehiko Sasa