Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.

Abstract: A deposition chamber includes a vacuum enclosure, an electrostatic chuck having a flat top surface located within a vacuum enclosure, a lift-and-rotation unit extending through or laterally surrounding the electrostatic chuck at a position that is laterally offset from a vertical axis passing through a geometrical center of the electrostatic chuck, a gas supply manifold configured to provide influx of gas into the vacuum enclosure, and a pumping port connected to the vacuum enclosure.

Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.

Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.

Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.

Abstract: An anisotropic etch apparatus contains an electrostatic chuck located in a vacuum enclosure and including a lower electrode, an upper electrode overlying the lower electrode and located in the vacuum enclosure, a main radio frequency (RF) power source configured to provide an RF bias voltage between the lower electrode and the upper electrode, and a plurality of conductive edge ring segments surrounding the electrostatic chuck and configured for at least one of independent vertical movement relative to the electrostatic chuck or for independently receiving a different RF bias voltage.

Abstract: A deposition chamber includes a vacuum enclosure, an electrostatic chuck having a flat top surface located within a vacuum enclosure, a lift-and-rotation unit extending through or laterally surrounding the electrostatic chuck at a position that is laterally offset from a vertical axis passing through a geometrical center of the electrostatic chuck, a gas supply manifold configured to provide influx of gas into the vacuum enclosure, and a pumping port connected to the vacuum enclosure.

Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.

Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.

Abstract: Memory stack structures can be formed through an alternating stack of insulating layers and spacer material layers that are formed as, or are subsequently replaced with, electrically conductive layers. The memory stack structures can be formed as rows having a first pitch. Additional insulating layers and at least one drain select level dielectric layer are formed over the alternating stack. Drain select level openings are formed in rows having a smaller second pitch. Partial replacement of the at least one drain select level dielectric layer forms spaced apart electrically conductive line structures that surround a respective plurality of drain select level openings. Drain select level channel portions are subsequently formed in respective drain select level openings.

Abstract: A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

Abstract: A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack structures located within memory openings through the stack. An epitaxial semiconductor pedestal is provided, which is in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and has a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack. The contact via structures for the semiconductor devices on the epitaxial semiconductor pedestal can extend can be less than the thickness of the stack.

Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.

Abstract: A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack structures located within memory openings through the stack. An epitaxial semiconductor pedestal is provided, which is in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and has a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack. The contact via structures for the semiconductor devices on the epitaxial semiconductor pedestal can extend can be less than the thickness of the stack.

Abstract: A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

Abstract: A method of making a monolithic three dimensional NAND string includes forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, etching the stack to form at least one opening in the stack, forming a buffer layer over a sidewall of the at least one opening, forming a charge storage material layer over the buffer layer, forming a tunnel dielectric layer over the charge storage material layer in the at least one opening, and forming a semiconductor channel material over the tunnel dielectric layer in the at least one opening. The method also includes selectively removing the second material layers without removing the first material layers and etching the buffer layer using the first material layers as a mask to form a plurality of separate discrete buffer segments and to expose portions of the charge storage material layer.

Abstract: The present invention provides a dielectric ceramic composition, a capacitor using the composition and the producing method, of having a lower dielectric loss and a stable characteristics in high frequency bandwidth, and enabling to use a base metal or a carbon-based material as an electrode material by allowing sintering at a low temperature, thereby resulting in lower cost. The dielectric ceramic composition according to present invention, is characterized in comprising a main component of formula SrxMg1-x(XryTi1-y) O3 (where 0.8≦x≦1; 0.9≦y≦1) to which MnO2 of 0.05-15 wt %, at least one of 0.001-5 wt % selected from the group consisting of Bi2O3, PbO and Sb2O3 and a glass component of 0.5-15 wt % are added based on the weight of the main component.

Abstract: The present invention provides a dielectric ceramic composition, a capacitor using the composition and the producing method, of having a lower dielectric loss and a stable characteristics in high frequency bandwidth, and enabling to use a base metal or a carbon-based material as an electrode material by allowing sintering at a low temperate, thereby resulting in lower cost. The dielectric ceramic composition according to present invention, is characterized in comprising a main component of formula SrxBa1−x(ZryTi1−y) O3 (where 0.8≦x≦1; 0.9≦y≦1) to which MnO2 of 0.05-15 wt %, at least one of 0.001-5 wt % selected from the group consisting of Bi2O3PbO and Sb2O3 and a glass component of 0.5-15 wt % are added based on the weight of the main component.

Abstract: The dielectric ceramic composition according to present invention, is characterized in comprising a component of formula SrxCa1−x(ZryTi1−y)03 (where 0.7≦x≦1; 0.9≦y≦1) to which MnO2 of 0.05-20 wt %, at least one of 0.001-5 wt % selected from tie group consisting of Bi2O3, PbO and Sb2O3 and a glass component of 0.5-10 wt % are added based on the weight of the main component.

Abstract: The present invention provides a dielectric ceramic composition, a capacitor using the composition and the producing method, of having a lower dielectric loss and a stable characteristics in high frequency bandwidth, and enabling to use a base metal or a carbon-based material as an electrode material by allowing sintering at a low temperate, thereby resulting in lower cost.