Abstract: According to one embodiment, a memory device includes a first silicon substrate, a second silicon substrate, and a memory cell array. A first CMOS circuit is formed on the first silicon substrate. The second silicon substrate is provided above the first silicon substrate in a stacking direction. A second CMOS circuit is formed on the second silicon substrate. The memory cell array is provided above the second silicon substrate in the stacking direction. The memory cell array is connected to the first CMOS circuit and the second CMOS circuit and includes a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate.

Abstract: A semiconductor memory device includes a substrate including a first region, as second region, a third region and a fourth regions, the first region including a memory cell array, the second region including a circuit for controlling the memory cell array, the third region separating the first region and the second region, and the fourth region surrounding the third region, a first transistor provided in the second region, a second transistor provided in the third region between the first region and the first transistor, a third transistor provided in the third region between the first transistor and the second transistor, and a first insulating layer including a first portion disposed above the first to third transistors, and a second portion disposed in contact with the substrate between the second transistor and the third transistor.

Abstract: In one embodiment, a semiconductor device includes a substrate, a lower pad provided above the substrate, and an upper pad provided on the lower pad. The lower pad includes a first pad and a plurality of first connection portions provided on the first pad, and the upper pad is provided on the plurality of first connection portions, or the upper pad includes a second pad and a plurality of second connection portions provided under the second pad, and the lower pad is provided under the plurality of second connection portions.

Abstract: A semiconductor memory device includes a substrate including a first region, as second region, a third region and a fourth regions, the first region including a memory cell array, the second region including a circuit for controlling the memory cell array, the third region separating the first region and the second region, and the fourth region surrounding the third region, a first transistor provided in the second region, a second transistor provided in the third region between the first region and the first transistor, a third transistor provided in the third region between the first transistor and the second transistor, and a first insulating layer including a first portion disposed above the first to third transistors, and a second portion disposed in contact with the substrate between the second transistor and the third transistor.

Abstract: In one embodiment, a semiconductor device includes a substrate, a lower pad provided above the substrate, and an upper pad provided on the lower pad. The lower pad includes a first pad and a plurality of first connection portions provided on the first pad, and the upper pad is provided on the plurality of first connection portions, or the upper pad includes a second pad and a plurality of second connection portions provided under the second pad, and the lower pad is provided under the plurality of second connection portions.

Abstract: A memory device includes a first conductive layer; a second conductive layer provided above the first conductive layer; a plurality of electrode layers stacked above the second conductive layer; a semiconductor pillar extending through the plurality of electrode layers and the second conductive layer, and connected to the first conductive layer; and a third conductive layer provided above the first conductive layer. The third conductive layer is positioned at a level substantially same as a level of the second conductive layer in an extension direction of the semiconductor pillar, and is made of a material same as a material of the second conductive layer. The third conductive layer is electrically isolated from the second conductive layer, and is electrically connected to the first conductive layer.

Abstract: A memory device includes a first conductive layer; a second conductive layer provided above the first conductive layer; a plurality of electrode layers stacked above the second conductive layer; a semiconductor pillar extending through the plurality of electrode layers and the second conductive layer, and connected to the first conductive layer; and a third conductive layer provided above the first conductive layer. The third conductive layer is positioned at a level substantially same as a level of the second conductive layer in an extension direction of the semiconductor pillar, and is made of a material same as a material of the second conductive layer. The third conductive layer is electrically isolated from the second conductive layer, and is electrically connected to the first conductive layer.

Abstract: A semiconductor memory device includes a substrate, a first stacked body provided in a first region on the substrate, a transistor formed in a second region of the substrate, and a block member provided between the first stacked body and the transistor. The first stacked body includes a plurality of first silicon oxide films and a plurality of electrode films stacked alternately one by one. Diffusion coefficient of hydrogen in the block member is lower than diffusion coefficient of hydrogen in silicon oxide.

Abstract: A semiconductor memory device includes a semiconductor substrate, a stepped structure including a stepped part in which a plurality of first insulating layers and conductive layers are alternately stacked on a main surface of the semiconductor substrate, the conductive layers including first, second, and third conductive layers, a second insulating layer which covers the stepped structure, a first contact interconnection which penetrates the second insulating layer and the first conductive layer in a thickness direction of the semiconductor substrate and is electrically connected to the second conductive layer, and a second contact interconnection which penetrates the second insulating layer and the second conductive layer in the thickness direction of the semiconductor substrate and is electrically connected to the third conductive layer.

Abstract: A display device includes a first electrode, an organic layer including a light emitting region, and a second electrode. The display device also includes a conductive layer electrically connected to the second electrode and including an opening corresponding to the light emitting region.

Abstract: A display unit includes: an oxide semiconductor layer configured to form a channel; a first layer having electrical insulation or electrical conductivity; and a second layer including a hydrogen absorbent and disposed between the oxide semiconductor layer and the first layer.

Abstract: A display unit includes: a first substrate including a plurality of light-emission devices in a display region, the plurality of light-emission devices each including an organic layer between a first electrode and a second electrode; a second substrate disposed to face the first substrate with the light-emission devices interposed therebetween; a first peripheral electrode provided on the second substrate and positioned outside the display region; a first wiring provided on the second substrate and configured to be electrically connected to the first peripheral electrode; and a first connection section configured to electrically connect the first wiring and each of the light-emission devices.

Abstract: A display unit includes: an oxide semiconductor layer configured to form a channel; a first layer having electrical insulation or electrical conductivity; and a second layer including a hydrogen absorbent and disposed between the oxide semiconductor layer and the first layer.

Abstract: A display unit includes: a first substrate including a plurality of light-emission devices in a display region, the plurality of light-emission devices each including an organic layer between a first electrode and a second electrode; a second substrate disposed to face the first substrate with the light-emission devices interposed therebetween; a first peripheral electrode provided on the second substrate and positioned outside the display region; a first wiring provided on the second substrate and configured to be electrically connected to the first peripheral electrode; and a first connection section configured to electrically connect the first wiring and each of the light-emission devices.

Abstract: An optical element covering member includes one or more optical elements, a support medium for supporting the one or more optical elements, and a covering member for covering the one or more optical elements and the support medium. At least one out of the one or more optical elements is a reflective polarizer, and the covering member has at least a region, through which the light inputted from a light source is emitted to a liquid crystal panel, the region having a phase difference lag of not more than 1/50 ? of a measured wavelength, with respect to an optical axis of the reflective polarizer.

Abstract: An illuminating device capable of decreasing not only in-plane luminance unevenness in the front face direction but also in-plane luminance unevenness when viewed from a diagonal direction is provided.

Abstract: An optical sheet laminate body includes: a first optical sheet having a top surface and a bottom surface, of which at least the top surface has asperities including projections and depressions; and a second optical sheet having a top surface and a bottom surface. Summits of the projections on the top surface of the first optical sheet are directly bonded, in a whole region facing the bottom surface of the second optical sheet, to the bottom surface of the second optical sheet without any intermediate material in between.

Abstract: An illuminating apparatus is provided and includes a plurality of point light sources in one plane and a first optical sheet and a second optical sheet overlapped in a region facing the plurality of point light sources. The plurality of point light sources are arranged in a first direction and also arranged in a second direction orthogonal to the first direction. The first optical sheet has a plurality of first three-dimensional structures extending in a direction parallel to the first direction and arranged in a direction parallel to the second direction. The second optical sheet has a plurality of second three-dimensional structures extending in a direction parallel to the second direction and arranged in a direction parallel to the first direction. Each of the second three-dimensional structures has a shape which generates a larger amount of return light from normal incident light as compared with the first three-dimensional structures.

Abstract: An optical sheet stack body includes two optical sheets disposed to overlap a plurality of point light sources arranged in a first direction and arranged in a second direction crossing the first direction. The optical sheets are disposed so that a long-side direction of the optical sheet crosses the first and second directions at an angle other than right angle. A first optical sheet disposed on the point light source side has a plurality of first three-dimensional structures extending in a direction parallel to or almost parallel to the first direction. A second optical sheet disposed on the side opposite to the point light source has a plurality of second three-dimensional structures extending in a direction parallel to or almost parallel to the second direction. The second three-dimensional structure has a shape by which return light is generated from normal incident light more than the first three-dimensional structure.

Abstract: There is provided an optical sheet stack which includes a first optical sheet having a large number of irregularities consecutively arranged on one surface thereof, and a second optical sheet stacked thereon. In the optical sheet stack, the second optical sheet has, on a bonding surface thereof, an adhesive layer bonded with apexes of the irregularities, and while assuming pitch of arrangement of the irregularities as P, and width of bonding of each apex of the irregularities bonded to the adhesive layer as Pw, the relation of 0<Pw/P?0.2 is satisfied.