Patents by Inventor Shigekazu Kimura
Shigekazu Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11444382Abstract: An antenna device includes an antenna element and a dummy antenna element. The antenna element is configured to construct a patch antennae. The dummy antenna is coupled to a ground layer by a conductive through portion which pass through a substrate in a thickness direction. A position of the conductive through portion with respect to the dummy antenna element is a first position on a straight line that divides an angle between a first straight line and a second straight line, or a second position in the neighborhood of the first position. The first straight pass through a first feed point and a center of dummy antenna element. The second straight passing through a second feed point and the center. The first feed point and the second feed point being feed points when the dummy antenna element generates circularly polarized waves.Type: GrantFiled: April 6, 2021Date of Patent: September 13, 2022Assignee: FUJITSU LIMITEDInventor: Shigekazu Kimura
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Patent number: 11387571Abstract: A slot antenna apparatus that includes a waveguide including a sidewall and having an extending direction, a slot provided on the sidewall, and a dielectric member that is attached to the waveguide and is slidable in the extending direction with respect to the slot, the dielectric member including a first section and a second section, the first section covering the slot at a first slide position, the second section covering the slot at a second slide position next to the first slide position, and the first section and the second section having different relative permittivities or different thicknesses with each other.Type: GrantFiled: January 27, 2021Date of Patent: July 12, 2022Assignee: FUJITSU LIMITEDInventors: Tomonori Sato, Shigekazu Kimura, Toshio Kawasaki, Yoji Ohashi
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Publication number: 20210367344Abstract: An antenna device includes an antenna element and a dummy antenna element. The antenna element is configured to construct a patch antennae. The dummy antenna is coupled to a ground layer by a conductive through portion which pass through a substrate in a thickness direction. A position of the conductive through portion with respect to the dummy antenna element is a first position on a straight line that divides an angle between a first straight line and a second straight line, or a second position in the neighborhood of the first position. The first straight pass through a first feed point and a center of dummy antenna element. The second straight passing through a second feed point and the center. The first feed point and the second feed point being feed points when the dummy antenna element generates circularly polarized waves.Type: ApplicationFiled: April 6, 2021Publication date: November 25, 2021Applicant: FUJITSU LIMITEDInventor: Shigekazu Kimura
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Publication number: 20210280987Abstract: A slot antenna apparatus that includes a waveguide including a sidewall and having an extending direction, a slot provided on the sidewall, and a dielectric member that is attached to the waveguide and is slidable in the extending direction with respect to the slot, the dielectric member including a first section and a second section, the first section covering the slot at a first slide position, the second section covering the slot at a second slide position next to the first slide position, and the first, section and the second section having different relative permittivities or different thicknesses with each other.Type: ApplicationFiled: January 27, 2021Publication date: September 9, 2021Applicant: FUJITSU LIMITEDInventors: TOMONORI SATO, Shigekazu Kimura, TOSHIO KAWASAKI, Yoji Ohashi
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Publication number: 20210005970Abstract: A slot antenna apparatus that includes a waveguide including a sidewall having an edge, a first slot provided on the sidewall, a second slot provided on the sidewall, and a first dielectric member mountable in the first slot or the second slot, the first dielectric member having a first dielectric property.Type: ApplicationFiled: June 18, 2020Publication date: January 7, 2021Applicant: FUJITSU LIMITEDInventor: Shigekazu KIMURA
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Patent number: 9577578Abstract: An amplifying device includes an amplifying element that amplifies a fundamental wave signal, and a short stub that has an electric length one fourth a wavelength of the fundamental wave signal, and is connected to a line on an output side of the amplifying element, the short stub being used as both a bias circuit that supplies a certain bias voltage to the amplifying element and a reflection circuit with respect to a harmonic signal that has a frequency twice a frequency of the fundamental wave signal, wherein the short stub has a pattern width that is larger than a pattern width of the line.Type: GrantFiled: November 18, 2015Date of Patent: February 21, 2017Assignee: FUJITSU LIMITEDInventor: Shigekazu Kimura
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Patent number: 9473072Abstract: An amplification device includes: a first circuit configured to: split an input signal into a first signal and a second signal, and adjust the first signal so that an amplitude of the first signal is less than an amplitude of the second signal by a reduced value, a first amplifier configured to amplify the adjusted first signal, a second amplifier configured to amplify the second signal, and a second circuit configured to: determine a reflection coefficient in case where the amplified second signal is a travelling wave and the amplified first signal is a reflected wave, and determine the reduced value based on the reflection coefficient.Type: GrantFiled: January 30, 2015Date of Patent: October 18, 2016Assignee: FUJITSU LIMITEDInventor: Shigekazu Kimura
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Publication number: 20160204744Abstract: An amplifying device includes an amplifying element that amplifies a fundamental wave signal, and a short stub that has an electric length one fourth a wavelength of the fundamental wave signal, and is connected to a line on an output side of the amplifying element, the short stub being used as both a bias circuit that supplies a certain bias voltage to the amplifying element and a reflection circuit with respect to a harmonic signal that has a frequency twice a frequency of the fundamental wave signal, wherein the short stub has a pattern width that is larger than a pattern width of the line.Type: ApplicationFiled: November 18, 2015Publication date: July 14, 2016Applicant: FUJITSU LIMITEDInventor: Shigekazu Kimura
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Patent number: 9319012Abstract: An amplifying apparatus, including an amplitude-phase conversion unit to separate an input signal into first and second signals, wherein a phase difference between the first and second signals depends on an amplitude of the input signal, a first amplifying unit, a first matching circuit including a main line and a first harmonic processing circuit, wherein a length of the line of the first harmonic processing circuit short-circuits a harmonic, a second amplifying unit, a second matching circuit including a main line and a second harmonic processing circuit, wherein a length of the line of the second harmonic processing circuit short-circuits a harmonic, and an output synthesis unit to synthesize outputs from the first and second matching circuits, wherein a distance from the first amplifying unit to the first harmonic processing circuit differs from a distance from the second amplifying unit to the second harmonic processing circuit.Type: GrantFiled: June 30, 2014Date of Patent: April 19, 2016Assignee: FUJITSU LIMITEDInventors: Toru Maniwa, Shigekazu Kimura, Nobuhisa Aoki
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Patent number: 9276536Abstract: An outphasing amplification apparatus includes: a signal decomposition unit for decomposing an input signal into a first signal and a second signal having predetermined amplitude values, respectively; a first amplification element for amplifying the first signal, and output a first amplification signal; a second amplification element for amplifying the second signal, and output a second amplification signal; and a combiner for combining the first amplified signal and the second amplified signal, wherein the combiner includes a first input transmission line having an impedance converter, a second input transmission line not having an impedance converter, and a combination unit configured to combine a signal produced by the first amplification signal passing through the first input transmission line to have been subjected to impedance conversion by the impedance converter, and a signal produced by the second amplification signal passing through the second input transmission line not having been subjected to impType: GrantFiled: June 2, 2014Date of Patent: March 1, 2016Assignee: FUJITSU LIMITEDInventor: Shigekazu Kimura
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Publication number: 20150222233Abstract: An amplification device includes: a first circuit configured to: split an input signal into a first signal and a second signal, and adjust the first signal so that an amplitude of the first signal is less than an amplitude of the second signal by a reduced value, a first amplifier configured to amplify the adjusted first signal, a second amplifier configured to amplify the second signal, and a second circuit configured to: determine a reflection coefficient in case where the amplified second signal is a travelling wave and the amplified first signal is a reflected wave, and determine the reduced value based on the reflection coefficient.Type: ApplicationFiled: January 30, 2015Publication date: August 6, 2015Inventor: Shigekazu KIMURA
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Patent number: 9059664Abstract: An amplifier includes a signal processing circuit configured to generate an orthogonal signal orthogonal to an input signal; a first D/A converter configured to convert the orthogonal signal into a first analog signal; a second D/A converter configured to convert the input signal into a second analog signal; and an analog computing circuit configured to generate a constant envelope signal based on the first analog signal from the first D/A converter and the second analog signal from the second D/A converter.Type: GrantFiled: October 30, 2012Date of Patent: June 16, 2015Assignee: FUJITSU LIMITEDInventors: Toru Maniwa, Shigekazu Kimura
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Publication number: 20150102859Abstract: An amplifying apparatus includes a decomposer, two amplifiers, a combiner, and a controller. The decomposer decomposes an input signal into two signals having different phases. The two amplifiers amplify the decomposed two signals, respectively. The combiner combines output of the amplifiers. The controller controls at least one of waveform information of at least one of the two signals and an operating state of the two amplifiers such that an output characteristic of the combiner matches a desired characteristic.Type: ApplicationFiled: September 10, 2014Publication date: April 16, 2015Inventors: TORU MANIWA, TOSHIO KAWASAKI, TOMONORI SATO, Shigekazu Kimura, NAOJI FUJINO
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Publication number: 20150008983Abstract: An amplifying apparatus, including an amplitude-phase conversion unit to separate an input signal into first and second signals, wherein a phase difference between the first and second signals depends on an amplitude of the input signal, a first amplifying unit, a first matching circuit including a main line and a first harmonic processing circuit, wherein a length of the line of the first harmonic processing circuit short-circuits a harmonic, a second amplifying unit, a second matching circuit including a main line and a second harmonic processing circuit, wherein a length of the line of the second harmonic processing circuit short-circuits a harmonic, and an output synthesis unit to synthesize outputs from the first and second matching circuits, wherein a distance from the first amplifying unit to the first harmonic processing circuit differs from a distance from the second amplifying unit to the second harmonic processing circuit.Type: ApplicationFiled: June 30, 2014Publication date: January 8, 2015Inventors: TORU MANIWA, Shigekazu Kimura, Nobuhisa Aoki
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Publication number: 20140368274Abstract: An outphasing amplification apparatus includes: a signal decomposition unit for decomposing an input signal into a first signal and a second signal having predetermined amplitude values, respectively; a first amplification element for amplifying the first signal, and output a first amplification signal; a second amplification element for amplifying the second signal, and output a second amplification signal; and a combiner for combining the first amplified signal and the second amplified signal, wherein the combiner includes a first input transmission line having an impedance converter, a second input transmission line not having an impedance converter, and a combination unit configured to combine a signal produced by the first amplification signal passing through the first input transmission line to have been subjected to impedance conversion by the impedance converter, and a signal produced by the second amplification signal passing through the second input transmission line not having been subjected to impType: ApplicationFiled: June 2, 2014Publication date: December 18, 2014Applicant: FUJITSU LIMITEDInventor: Shigekazu Kimura
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Publication number: 20140292405Abstract: An amplification device includes: an amplitude adjustment circuit configured to adjust an amplitude level of an input signal so as to keep the amplitude level within a given range; an amplifier configured to amplify the adjusted signal; and a circuitry configured to change an amplitude level of the amplified signal, based on the amplitude level of the input signal and a first distortion compensation corresponding to the amplitude level of the input signal.Type: ApplicationFiled: March 25, 2014Publication date: October 2, 2014Applicant: FUJITSU LIMITEDInventors: Takeshi TAKANO, Shigekazu KIMURA, Ken TAMANOI, Masakazu KOJIMA, Toru MANIWA, Yasuyuki OISHI, Michiharu NAKAMURA, Kazuo NAGATANI
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Publication number: 20140285262Abstract: A control device of a power amplifier includes: a limiter configured to limit a level of an input signal to the power amplifier; and a control unit configured to, when the limiter operates, make an operation voltage of the power amplifier invariable and control load of an output matching circuit of the power amplifier based on an amplitude of the input signal, and, when the limiter does not operate, to make the load of the output matching circuit invariable and control the operation voltage of the power amplifier.Type: ApplicationFiled: November 26, 2013Publication date: September 25, 2014Applicant: FUJITSU LIMITEDInventors: Masakazu KOJIMA, Shigekazu Kimura, Takeshi Takano, Toru Maniwa, Ken Tamanoi
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Patent number: 8836432Abstract: An amplifier includes an amplifying element that amplifies an input signal; an output terminal that outputs the signal amplified by the amplifying element; a matching circuit disposed in series between the amplifying element and the output terminal, and performing impedance matching; an impedance converter disposed in series between the amplifying element and the matching circuit or between the matching circuit and the output terminal; and a first resonator and a second resonator connected at the ends of the impedance converter.Type: GrantFiled: January 13, 2013Date of Patent: September 16, 2014Assignee: Fujitsu LimitedInventors: Toru Maniwa, Shigekazu Kimura
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Patent number: 8686794Abstract: An amplifying apparatus includes a first amplifier that amplifies a first signal of a constant amplitude; a second amplifier that amplifies a second signal identical in amplitude and differing in phase with respect to the first signal; a first transmission line of which, a first end is connected to an output terminal of the first amplifier; a second transmission line differing in length with respect to the first transmission line and of which, a first end is connected to an output terminal of the second amplifier and a second end is connected to a second end of the first transmission line; and an amplitude balance adjusting element connected to the first or the second transmission line. The amplifying apparatus outputs from a connection node of the first and the second transmission lines, a signal that is a combination of output signals of the first amplifier and of the second amplifier.Type: GrantFiled: May 20, 2013Date of Patent: April 1, 2014Assignee: Fujitsu LimitedInventor: Shigekazu Kimura
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Publication number: 20140055199Abstract: A power amplification device, includes: an amplifier to amplify an input signal; a switched capacitor, provided at an output stage of the amplifier, to change capacitance based on a first control signal; a matching unit, provided at the output stage of the amplifier and including a varactor pair in which two varactor diodes are coupled in series or a varactor pair in which two varactor diodes are coupled in parallel, to change capacitance based on a second control signal; a detection circuit to detect power of the input signal; a quantization circuit to quantize a detected power value, form a quantized bit string having a high-order bit group and a low-order bit group, and output the high-order bit group as the first control signal to the switched capacitor; and a conversion circuit to convert the low-order bit group into an analog value and form the second control signal.Type: ApplicationFiled: June 6, 2013Publication date: February 27, 2014Inventors: Takeshi TAKANO, Masakazu Kojima, Michiharu Nakamura, Toru Maniwa, Shigekazu Kimura, Ken Tamanoi