Patents by Inventor Shigekazu Kimura

Shigekazu Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11444382
    Abstract: An antenna device includes an antenna element and a dummy antenna element. The antenna element is configured to construct a patch antennae. The dummy antenna is coupled to a ground layer by a conductive through portion which pass through a substrate in a thickness direction. A position of the conductive through portion with respect to the dummy antenna element is a first position on a straight line that divides an angle between a first straight line and a second straight line, or a second position in the neighborhood of the first position. The first straight pass through a first feed point and a center of dummy antenna element. The second straight passing through a second feed point and the center. The first feed point and the second feed point being feed points when the dummy antenna element generates circularly polarized waves.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: September 13, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Kimura
  • Patent number: 11387571
    Abstract: A slot antenna apparatus that includes a waveguide including a sidewall and having an extending direction, a slot provided on the sidewall, and a dielectric member that is attached to the waveguide and is slidable in the extending direction with respect to the slot, the dielectric member including a first section and a second section, the first section covering the slot at a first slide position, the second section covering the slot at a second slide position next to the first slide position, and the first section and the second section having different relative permittivities or different thicknesses with each other.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: July 12, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Tomonori Sato, Shigekazu Kimura, Toshio Kawasaki, Yoji Ohashi
  • Publication number: 20210367344
    Abstract: An antenna device includes an antenna element and a dummy antenna element. The antenna element is configured to construct a patch antennae. The dummy antenna is coupled to a ground layer by a conductive through portion which pass through a substrate in a thickness direction. A position of the conductive through portion with respect to the dummy antenna element is a first position on a straight line that divides an angle between a first straight line and a second straight line, or a second position in the neighborhood of the first position. The first straight pass through a first feed point and a center of dummy antenna element. The second straight passing through a second feed point and the center. The first feed point and the second feed point being feed points when the dummy antenna element generates circularly polarized waves.
    Type: Application
    Filed: April 6, 2021
    Publication date: November 25, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Shigekazu Kimura
  • Publication number: 20210280987
    Abstract: A slot antenna apparatus that includes a waveguide including a sidewall and having an extending direction, a slot provided on the sidewall, and a dielectric member that is attached to the waveguide and is slidable in the extending direction with respect to the slot, the dielectric member including a first section and a second section, the first section covering the slot at a first slide position, the second section covering the slot at a second slide position next to the first slide position, and the first, section and the second section having different relative permittivities or different thicknesses with each other.
    Type: Application
    Filed: January 27, 2021
    Publication date: September 9, 2021
    Applicant: FUJITSU LIMITED
    Inventors: TOMONORI SATO, Shigekazu Kimura, TOSHIO KAWASAKI, Yoji Ohashi
  • Publication number: 20210005970
    Abstract: A slot antenna apparatus that includes a waveguide including a sidewall having an edge, a first slot provided on the sidewall, a second slot provided on the sidewall, and a first dielectric member mountable in the first slot or the second slot, the first dielectric member having a first dielectric property.
    Type: Application
    Filed: June 18, 2020
    Publication date: January 7, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Shigekazu KIMURA
  • Patent number: 9577578
    Abstract: An amplifying device includes an amplifying element that amplifies a fundamental wave signal, and a short stub that has an electric length one fourth a wavelength of the fundamental wave signal, and is connected to a line on an output side of the amplifying element, the short stub being used as both a bias circuit that supplies a certain bias voltage to the amplifying element and a reflection circuit with respect to a harmonic signal that has a frequency twice a frequency of the fundamental wave signal, wherein the short stub has a pattern width that is larger than a pattern width of the line.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: February 21, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Kimura
  • Patent number: 9473072
    Abstract: An amplification device includes: a first circuit configured to: split an input signal into a first signal and a second signal, and adjust the first signal so that an amplitude of the first signal is less than an amplitude of the second signal by a reduced value, a first amplifier configured to amplify the adjusted first signal, a second amplifier configured to amplify the second signal, and a second circuit configured to: determine a reflection coefficient in case where the amplified second signal is a travelling wave and the amplified first signal is a reflected wave, and determine the reduced value based on the reflection coefficient.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 18, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Kimura
  • Publication number: 20160204744
    Abstract: An amplifying device includes an amplifying element that amplifies a fundamental wave signal, and a short stub that has an electric length one fourth a wavelength of the fundamental wave signal, and is connected to a line on an output side of the amplifying element, the short stub being used as both a bias circuit that supplies a certain bias voltage to the amplifying element and a reflection circuit with respect to a harmonic signal that has a frequency twice a frequency of the fundamental wave signal, wherein the short stub has a pattern width that is larger than a pattern width of the line.
    Type: Application
    Filed: November 18, 2015
    Publication date: July 14, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Shigekazu Kimura
  • Patent number: 9319012
    Abstract: An amplifying apparatus, including an amplitude-phase conversion unit to separate an input signal into first and second signals, wherein a phase difference between the first and second signals depends on an amplitude of the input signal, a first amplifying unit, a first matching circuit including a main line and a first harmonic processing circuit, wherein a length of the line of the first harmonic processing circuit short-circuits a harmonic, a second amplifying unit, a second matching circuit including a main line and a second harmonic processing circuit, wherein a length of the line of the second harmonic processing circuit short-circuits a harmonic, and an output synthesis unit to synthesize outputs from the first and second matching circuits, wherein a distance from the first amplifying unit to the first harmonic processing circuit differs from a distance from the second amplifying unit to the second harmonic processing circuit.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: April 19, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Toru Maniwa, Shigekazu Kimura, Nobuhisa Aoki
  • Patent number: 9276536
    Abstract: An outphasing amplification apparatus includes: a signal decomposition unit for decomposing an input signal into a first signal and a second signal having predetermined amplitude values, respectively; a first amplification element for amplifying the first signal, and output a first amplification signal; a second amplification element for amplifying the second signal, and output a second amplification signal; and a combiner for combining the first amplified signal and the second amplified signal, wherein the combiner includes a first input transmission line having an impedance converter, a second input transmission line not having an impedance converter, and a combination unit configured to combine a signal produced by the first amplification signal passing through the first input transmission line to have been subjected to impedance conversion by the impedance converter, and a signal produced by the second amplification signal passing through the second input transmission line not having been subjected to imp
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: March 1, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Kimura
  • Publication number: 20150222233
    Abstract: An amplification device includes: a first circuit configured to: split an input signal into a first signal and a second signal, and adjust the first signal so that an amplitude of the first signal is less than an amplitude of the second signal by a reduced value, a first amplifier configured to amplify the adjusted first signal, a second amplifier configured to amplify the second signal, and a second circuit configured to: determine a reflection coefficient in case where the amplified second signal is a travelling wave and the amplified first signal is a reflected wave, and determine the reduced value based on the reflection coefficient.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 6, 2015
    Inventor: Shigekazu KIMURA
  • Patent number: 9059664
    Abstract: An amplifier includes a signal processing circuit configured to generate an orthogonal signal orthogonal to an input signal; a first D/A converter configured to convert the orthogonal signal into a first analog signal; a second D/A converter configured to convert the input signal into a second analog signal; and an analog computing circuit configured to generate a constant envelope signal based on the first analog signal from the first D/A converter and the second analog signal from the second D/A converter.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: June 16, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Toru Maniwa, Shigekazu Kimura
  • Publication number: 20150102859
    Abstract: An amplifying apparatus includes a decomposer, two amplifiers, a combiner, and a controller. The decomposer decomposes an input signal into two signals having different phases. The two amplifiers amplify the decomposed two signals, respectively. The combiner combines output of the amplifiers. The controller controls at least one of waveform information of at least one of the two signals and an operating state of the two amplifiers such that an output characteristic of the combiner matches a desired characteristic.
    Type: Application
    Filed: September 10, 2014
    Publication date: April 16, 2015
    Inventors: TORU MANIWA, TOSHIO KAWASAKI, TOMONORI SATO, Shigekazu Kimura, NAOJI FUJINO
  • Publication number: 20150008983
    Abstract: An amplifying apparatus, including an amplitude-phase conversion unit to separate an input signal into first and second signals, wherein a phase difference between the first and second signals depends on an amplitude of the input signal, a first amplifying unit, a first matching circuit including a main line and a first harmonic processing circuit, wherein a length of the line of the first harmonic processing circuit short-circuits a harmonic, a second amplifying unit, a second matching circuit including a main line and a second harmonic processing circuit, wherein a length of the line of the second harmonic processing circuit short-circuits a harmonic, and an output synthesis unit to synthesize outputs from the first and second matching circuits, wherein a distance from the first amplifying unit to the first harmonic processing circuit differs from a distance from the second amplifying unit to the second harmonic processing circuit.
    Type: Application
    Filed: June 30, 2014
    Publication date: January 8, 2015
    Inventors: TORU MANIWA, Shigekazu Kimura, Nobuhisa Aoki
  • Publication number: 20140368274
    Abstract: An outphasing amplification apparatus includes: a signal decomposition unit for decomposing an input signal into a first signal and a second signal having predetermined amplitude values, respectively; a first amplification element for amplifying the first signal, and output a first amplification signal; a second amplification element for amplifying the second signal, and output a second amplification signal; and a combiner for combining the first amplified signal and the second amplified signal, wherein the combiner includes a first input transmission line having an impedance converter, a second input transmission line not having an impedance converter, and a combination unit configured to combine a signal produced by the first amplification signal passing through the first input transmission line to have been subjected to impedance conversion by the impedance converter, and a signal produced by the second amplification signal passing through the second input transmission line not having been subjected to imp
    Type: Application
    Filed: June 2, 2014
    Publication date: December 18, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Shigekazu Kimura
  • Publication number: 20140292405
    Abstract: An amplification device includes: an amplitude adjustment circuit configured to adjust an amplitude level of an input signal so as to keep the amplitude level within a given range; an amplifier configured to amplify the adjusted signal; and a circuitry configured to change an amplitude level of the amplified signal, based on the amplitude level of the input signal and a first distortion compensation corresponding to the amplitude level of the input signal.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi TAKANO, Shigekazu KIMURA, Ken TAMANOI, Masakazu KOJIMA, Toru MANIWA, Yasuyuki OISHI, Michiharu NAKAMURA, Kazuo NAGATANI
  • Publication number: 20140285262
    Abstract: A control device of a power amplifier includes: a limiter configured to limit a level of an input signal to the power amplifier; and a control unit configured to, when the limiter operates, make an operation voltage of the power amplifier invariable and control load of an output matching circuit of the power amplifier based on an amplitude of the input signal, and, when the limiter does not operate, to make the load of the output matching circuit invariable and control the operation voltage of the power amplifier.
    Type: Application
    Filed: November 26, 2013
    Publication date: September 25, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Masakazu KOJIMA, Shigekazu Kimura, Takeshi Takano, Toru Maniwa, Ken Tamanoi
  • Patent number: 8836432
    Abstract: An amplifier includes an amplifying element that amplifies an input signal; an output terminal that outputs the signal amplified by the amplifying element; a matching circuit disposed in series between the amplifying element and the output terminal, and performing impedance matching; an impedance converter disposed in series between the amplifying element and the matching circuit or between the matching circuit and the output terminal; and a first resonator and a second resonator connected at the ends of the impedance converter.
    Type: Grant
    Filed: January 13, 2013
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventors: Toru Maniwa, Shigekazu Kimura
  • Patent number: 8686794
    Abstract: An amplifying apparatus includes a first amplifier that amplifies a first signal of a constant amplitude; a second amplifier that amplifies a second signal identical in amplitude and differing in phase with respect to the first signal; a first transmission line of which, a first end is connected to an output terminal of the first amplifier; a second transmission line differing in length with respect to the first transmission line and of which, a first end is connected to an output terminal of the second amplifier and a second end is connected to a second end of the first transmission line; and an amplitude balance adjusting element connected to the first or the second transmission line. The amplifying apparatus outputs from a connection node of the first and the second transmission lines, a signal that is a combination of output signals of the first amplifier and of the second amplifier.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: April 1, 2014
    Assignee: Fujitsu Limited
    Inventor: Shigekazu Kimura
  • Publication number: 20140055199
    Abstract: A power amplification device, includes: an amplifier to amplify an input signal; a switched capacitor, provided at an output stage of the amplifier, to change capacitance based on a first control signal; a matching unit, provided at the output stage of the amplifier and including a varactor pair in which two varactor diodes are coupled in series or a varactor pair in which two varactor diodes are coupled in parallel, to change capacitance based on a second control signal; a detection circuit to detect power of the input signal; a quantization circuit to quantize a detected power value, form a quantized bit string having a high-order bit group and a low-order bit group, and output the high-order bit group as the first control signal to the switched capacitor; and a conversion circuit to convert the low-order bit group into an analog value and form the second control signal.
    Type: Application
    Filed: June 6, 2013
    Publication date: February 27, 2014
    Inventors: Takeshi TAKANO, Masakazu Kojima, Michiharu Nakamura, Toru Maniwa, Shigekazu Kimura, Ken Tamanoi