Patents by Inventor Shigekazu Kogita
Shigekazu Kogita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190391762Abstract: A memory controller includes an address converter configured to convert an address designated by a host device for writing and reading into a physical address of a non-volatile memory, and an invalid-area manager configured to manage an invalid area of the non-volatile memory, the address converter making no reference to the invalid area, and, upon receipt of an invalid-data read command from the host device, data in the invalid area, managed by the invalid-area manager, of the non-volatile memory is output to the host device.Type: ApplicationFiled: June 14, 2019Publication date: December 26, 2019Inventors: Shigekazu KOGITA, Toshiyuki HONDA, Hirokazu SO, Masato SUTO
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Publication number: 20190335062Abstract: A memory controller includes a data discard controller, calculates a physical address of discard object data designated by a logical address by a host device, and registers the calculated physical address as discard object data information. With respect to a predetermined command from the host device, the data discard controller outputs current discard object data information to the host device. When no command is received from the host device, the data discard controller physically erases the discard object data on the basis of the discard object data information.Type: ApplicationFiled: April 9, 2019Publication date: October 31, 2019Inventors: Hirokazu SOU, Toshiyuki HONDA, Shigekazu KOGITA, Masato SUTO
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Patent number: 10324664Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.Type: GrantFiled: March 24, 2016Date of Patent: June 18, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hirokazu So, Toshiyuki Honda, Shigekazu Kogita
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Patent number: 9965202Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.Type: GrantFiled: March 24, 2016Date of Patent: May 8, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shigekazu Kogita, Hirokazu So, Toshiyuki Honda
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Publication number: 20160283150Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.Type: ApplicationFiled: March 24, 2016Publication date: September 29, 2016Inventors: Shigekazu KOGITA, Hirokazu SO, Toshiyuki HONDA
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Publication number: 20160283163Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.Type: ApplicationFiled: March 24, 2016Publication date: September 29, 2016Inventors: Hirokazu SO, Toshiyuki HONDA, Shigekazu KOGITA
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Patent number: 9092361Abstract: It is possible to accurately detect a physical block which has caused a fixture defect in a flash memory so as to limit the use of the physical block. By recording a history of generation of a physical block error and a history of physical erasing in an ECC error record, it is judged whether the error which has occurred is accidental or caused by a fixture defect. When no error is caused in the data written by physical erasing after a first read error occurrence, the first error is accidental and if another error is caused, the error is judged to be caused by a fixture defect. By using such an ECC error record, it is possible to accurately judge whether the error is accidental or caused by a fixture defect. By eliminating use of the physical block judged to have a fixture defect, it is possible to reduce read errors.Type: GrantFiled: July 13, 2006Date of Patent: July 28, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Toshiyuki Honda, Kunihiro Maki, Shigekazu Kogita
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Patent number: 8914579Abstract: Provided is a method that, in the case of managing areas of a non-volatile memory of an information recording module by a file system, increases the speed of processing for writing file data and file system management information, and furthermore prevents a decrease in the rewriting lifetime of the non-volatile memory. The information recording module (2) is provided with a page cache control unit (217) that stores page cache information (224) in the non-volatile memory (22) of the information recording module (2) and performs control such that a specific physical block is used as a cache when writing small-sized data. Also, an access module (1) is provided with a page cache information setting unit (104) that sets information necessary for page cache control in the information recording module (2).Type: GrantFiled: February 27, 2009Date of Patent: December 16, 2014Assignee: Panasonic CorporationInventors: Takuji Maeda, Shigekazu Kogita, Shinji Inoue, Hiroki Etoh, Makoto Ochi, Masahiro Nakamura
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Patent number: 8307149Abstract: A nonvolatile memory device (101) includes a plurality of physical blocks, each of which is provide with a nonvolatile memory (103), a logic/physical address conversion table, a temporary block and a temporary table. The nonvolatile memory (103) includes a plurality of pages which are predetermined writing units, respectively. The logical-physical address conversion table (106) stores correspondence information between logic addresses and physical addresses of data to be stored in the physical blocks. The temporary block is a physical block to store data that are smaller in size than those of the page. The temporary table (107) stores correspondence information between logic addresses and physical addresses with respect to data to be stored in the temporary block.Type: GrantFiled: December 7, 2006Date of Patent: November 6, 2012Assignee: Panasonic CorporationInventors: Toshiyuki Honda, Hirokazu So, Shigekazu Kogita, Masayuki Toyama, Seiji Nakamura, Masato Suto, Manabu Inoue
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Publication number: 20100332717Abstract: Provided is a method that, in the case of managing areas of a non-volatile memory of an information recording module by a file system, increases the speed of processing for writing file data and file system management information, and furthermore prevents a decrease in the rewriting lifetime of the non-volatile memory. The information recording module (2) is provided with a page cache control unit (217) that stores page cache information (224) in the non-volatile memory (22) of the information recording module (2) and performs control such that a specific physical block is used as a cache when writing small-sized data. Also, an access module (1) is provided with a page cache information setting unit (104) that sets information necessary for page cache control in the information recording module (2).Type: ApplicationFiled: February 27, 2009Publication date: December 30, 2010Inventors: Takuji Maeda, Shigekazu Kogita, Shinji Inoue, Hiroki Etoh, Makoto Ochi, Masahiro Nakamura
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Publication number: 20100180072Abstract: A file system (105) and a nonvolatile memory device (101) notify each other of the cluster size and the logic block size respectively in advance. In writing, the file system notifies the nonvolatile memory device of data as to which cluster of the file system can be discarded in the logical block of the nonvolatile memory device. With this, the nonvolatile memory device can avoid the copy of data at the writing, so that the nonvolatile memory device is not required to continuously keep data of an unnecessary file.Type: ApplicationFiled: June 9, 2008Publication date: July 15, 2010Inventors: Shigekazu Kogita, Takuji Maeda, Hiroki Etoh
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Publication number: 20090055680Abstract: It is possible to accurately detect a physical block which has caused a fixture defect in a flash memory so as to limit the use of the physical block. By recording a history of generation of a physical block error and a history of physical erasing in an ECC error record, it is judged whether the error which has occurred is accidental or caused by a fixture defect. When no error is caused in the data written by physical erasing after a first read error occurrence, the first error is accidental and if another error is caused, the error is judged to be caused by a fixture defect. By using such an ECC error record, it is possible to accurately judge whether the error is accidental or caused by a fixture defect. By eliminating use of the physical block judged to have a fixture defect, it is possible to reduce read errors.Type: ApplicationFiled: July 13, 2006Publication date: February 26, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshiyuki Honda, Kunihiro Maki, Shigekazu Kogita
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Publication number: 20090049229Abstract: A nonvolatile memory device (101) includes a plurality of physical blocks, each of which is provide with a nonvolatile memory (103), a logic/physical address conversion table, a temporary block and a temporary table. The nonvolatile memory (103) includes a plurality of pages which are predetermined writing units, respectively. The logical-physical address conversion table (106) stores correspondence information between logic addresses and physical addresses of data to be stored in the physical blocks. The temporary block is a physical block to store data that are smaller in size than those of the page. The temporary table (107) stores correspondence information between logic addresses and physical addresses with respect to data to be stored in the temporary block.Type: ApplicationFiled: December 7, 2006Publication date: February 19, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshiyuki Honda, Hirokazu So, Shigekazu Kogita, Masayuki Toyama, Seiji Nakamura, Masato Suto, Manabu Inoue
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Patent number: 7039781Abstract: A flash memory system is disclosed. The flash memory system includes a flash memory comprising more than one physical block and more than one page, where each page can be in an enabled state, a blank state or a disabled state. In use, a merge control section reads data on an enabled page from a predetermined physical block using a read section, and writes the data onto a blank page using a write section, thereby copying the data on the enabled page onto the blank page. A merge control section then disables the enabled page using a page-disabling section. When the copying of the data from all the enabled pages in the predetermined physical block is finished, the merge control section collectively erases all the data in the physical block using an erase section.Type: GrantFiled: July 23, 2002Date of Patent: May 2, 2006Assignee: Matsushtia Electric Industrial Co., Ltd.Inventors: Kazuya Iwata, Shigekazu Kogita, Akio Takeuchi
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Patent number: 6879528Abstract: A control method of nonvolatile memory is provided, wherein it does not happen that data which ought to have been erased are not erased, or data which ought to have been written are lost even if a forced interruption takes place due to shutdown of a power source for a memory device, a reset command, or the like occurs when data are written in a last page of a block, the block is validated by setting the block data validation flag provided in the redundant area of the last page of block 0 (valid). Furthermore, a counter judges whether the data is new or old, and data can be protected even if the above-mentioned solution cannot be implemented.Type: GrantFiled: June 24, 2002Date of Patent: April 12, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akio Takeuchi, Shigekazu Kogita, Kazuya Iwata
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Publication number: 20040193774Abstract: In a flush memory system according to the present invention, a merge control section (3f) reads data on an enabled page from a predetermined physical block using a read section (3b), and writes the data onto a blank page using a write section (3c), thereby copying the data on the enabled page onto the blank page. Then, the merge control section disables the source, enabled page using a page-disabling section (3e). When finishing the copying of data on all the enabled pages in the predetermined physical block, the merge control section collectively erases all the data in the physical block using an erase section (3d).Type: ApplicationFiled: December 24, 2003Publication date: September 30, 2004Inventors: Kazuya Iwata, Shigekazu Kogita, Akio Takeuchi
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Publication number: 20030189860Abstract: A control method of nonvolatile memory, wherein it does not happen that data which ought to have been erased are not erased or data which ought to have been written are lost even in the case where forced interruption takes place due to shutdown of power source for memory device, reset command or the like, is provided.Type: ApplicationFiled: February 27, 2003Publication date: October 9, 2003Inventors: Akio Takeuchi, Shigekazu Kogita, Kazuya Iwata