Abstract: Systems and methods for controlling engine idle speed based on electrical load are provided. A system includes a logic device configured to perform various operations for controlling an idle speed of an engine. The logic device is configured to determine a state of charge (SOC) of a battery, a maximum output of an alternator at a current idle speed of an engine, and a load on the alternator. The logic device is further configured to initiate an increased idle speed of the engine based on the determined SOC of the battery and based on the load being greater than the maximum output. The logic device is further configured to initiate a decreased idle speed of the engine based on the SOC being less than an SOC threshold. Associated methods are also provided.

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes.

Abstract: To provide a semiconductor device in which a terminal for outputting an electric signal to outside is further miniaturized, and a manufacturing method of the semiconductor device. A semiconductor device provided with a first chip formed by stacking a first substrate and a first wiring layer, the first chip including a sensor element, a second chip formed by stacking a second substrate and a second wiring layer, the second chip bonded to the first chip such that the first wiring layer faces the second wiring layer, and at least one or more through-hole vias electrically connected to the second wiring layer and penetrating the second substrate to protrude from a surface of the second chip opposed to a surface on which the first chip is stacked.

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes.

Abstract: A semiconductor memory, such as Dynamic Random Access Memory (DRAM), is provided for replacing a defective memory cell with a spare memory cell. The DRAM includes a main section which has a memory cell array with a plurality of memory cells arranged in an array. A spare section having a spare memory cell array also includes a plurality of memory cells arranged in an array. An address decoder specifies addresses, respectively, of the main section array and the spare section array. A defective bit replacement control circuit is connected to the address decoder and includes a plurality of electrically rewritable nonvolatile memory cells. The address decoder conducts a change-over operation for specifying an address of the first or second arrays according to a storage state, i.e., contents, of electrically rewritable nonvolatile memory cells.

Abstract: A DRAM includes a main section including a DRAM memory cell array including a plurality of DRAM cells arranged in an array, a spare section including a Spare DRAM memory cell array including a plurality of DRAM memory cells arranged in an array, an address decoder for specifying addresses respectively of the DRAM memory cell array and the spare DRAM memory cell array, and a defective bit replacement control circuit which is connected to the address decoder and which includes a plurality of electrically rewritable nonvolatile memory cells.