Patents by Inventor Shigeki Furuya
Shigeki Furuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170049842Abstract: Provided is a raw material for a food additive which promotes the intracerebral release of monoamines such as dopamine and noradrenaline, and imparts a function to prevent cranial nerve disease and a function to improve brain function to foods, by being added to said foods. This method involves using as a food additive an oligopeptide mixture containing dipeptides or tripeptides having tyrosine or phenylalanine as constituent amino acids, in order to produce foods to prevent cranial nerve disease or foods to improve brain function.Type: ApplicationFiled: April 28, 2015Publication date: February 23, 2017Applicant: FUJI OIL HOLDINGS INC.Inventors: Shigeki FURUYA, Toshiro MATSUI, Mitsuru TANAKA, Motohiro MAEBUCHI, Toshihiro NAKAMORI, Hitoshi FURUTA
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Publication number: 20080237646Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.Type: ApplicationFiled: May 29, 2008Publication date: October 2, 2008Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
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Patent number: 7394156Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.Type: GrantFiled: January 25, 2005Date of Patent: July 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
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Patent number: 7170115Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.Type: GrantFiled: October 5, 2001Date of Patent: January 30, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
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Patent number: 7061320Abstract: A differential amplifier according to the present invention comprises, in addition to a differential amplifier circuit and an output-stage amplifier circuit, a first source follower circuit for buffering a first output signal of the differential amplifier circuit, a second source follower circuit for buffering the first output signal of the differential amplifier circuit, and a source ground amplifier circuit, to a source of which an output terminal of the second source follower circuit is connected, and driven by a second output signal of the differential amplifier circuit, wherein a first-polar transistor in the output-stage amplifier circuit is driven by an output signal of the first source follower circuit, and the second-polar transistor is driven by an output signal of the source ground amplifier circuit.Type: GrantFiled: July 20, 2004Date of Patent: June 13, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Kimura, Shigeki Furuya
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Publication number: 20050127406Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.Type: ApplicationFiled: January 25, 2005Publication date: June 16, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
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Publication number: 20050017808Abstract: A differential amplifier according to the present invention comprises, in addition to a differential amplifier circuit and an output-stage amplifier circuit, a first source follower circuit for buffering a first output signal of the differential amplifier circuit, a second source follower circuit for buffering the first output signal of the differential amplifier circuit, and a source ground amplifier circuit, to a source of which an output terminal of the second source follower circuit is connected, and driven by a second output signal of the differential amplifier circuit, wherein a first-polar transistor in the output-stage amplifier circuit is driven by an output signal of the first source follower circuit, and the second-polar transistor is driven by an output signal of the source ground amplifier circuit.Type: ApplicationFiled: July 20, 2004Publication date: January 27, 2005Inventors: Hiroshi Kimura, Shigeki Furuya
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Patent number: 6800883Abstract: In a CMOS basic cell used in fabrication of a gate array semiconductor integrated circuit, each of the gate and the diffusion region of a P-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. Similarly, each of the gate and the diffusion region of an N-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. In the case where a semiconductor integrated circuit is fabricated by arranging basic cells having the same structure on the right and left hand sides of this basic cell, the basic cells adjacent to each other are overlapped by portions thereof corresponding to one grid, so that the portions in the hooked shapes can be alternately inlaid with each other. Accordingly, the semiconductor integrated circuit attains a smaller layout area.Type: GrantFiled: August 7, 2001Date of Patent: October 5, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shigeki Furuya, Hisaki Watanabe, Atsushi Mototani
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Patent number: 6407571Abstract: A voltage detecting circuit for detecting a state of a first voltage includes a detection voltage generating circuit for generating a detection voltage depending on the first voltage, a reference voltage generating circuit for generating a reference voltage, a comparison circuit for comparing the detection voltage with the reference voltage and outputting a result of the comparison as a detection signal, and a control circuit for controlling at least one of the detection voltage generating circuit, the reference voltage generating circuit, and the comparison circuit so that at least one of these circuits operates intermittently.Type: GrantFiled: April 12, 2000Date of Patent: June 18, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shigeki Furuya, Koji Oka
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Publication number: 20020043668Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.Type: ApplicationFiled: October 5, 2001Publication date: April 18, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
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Publication number: 20020034110Abstract: In a CMOS basic cell used in fabrication of a gate array semiconductor integrated circuit, each of the gate and the diffusion region of a P-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. Similarly, each of the gate and the diffusion region of an N-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. In the case where a semiconductor integrated circuit is fabricated by arranging basic cells having the same structure on the right and left hand sides of this basic cell, the basic cells adjacent to each other are overlapped by portions thereof corresponding to one grid, so that the portions in the hooked shapes can be alternately inlaid with each other. Accordingly, the semiconductor integrated circuit attains a smaller layout area.Type: ApplicationFiled: August 7, 2001Publication date: March 21, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shigeki Furuya, Hisaki Watanabe, Atsushi Mototani
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Patent number: 6310097Abstract: An agent for enhancing cell survival of central nerve cells, which comprises a substance selected from the group consisting of L-serine, glycine, and fatty acid compounds thereof as an active ingredient, and a medicament for preventive and/or therapeutic treatment of cerebral dysfunction which comprises said substance as an active ingredient. The substance has an action for protecting cerebral cells to suppress cell death and prolong cell life. For example, cerebral cell death caused by cerebral edema or the raise of intracerebral temperature due to cerebral hemorrhage, cerebral infarction head injury and the like can be suppressed.Type: GrantFiled: April 17, 2000Date of Patent: October 30, 2001Assignees: Riken, Taisho Pharmaceutical Co., Ltd.Inventors: Jyunya Mitoma, Shigeki Furuya, Yoshio Hirabayashi