Patents by Inventor Shigeki Hayashida

Shigeki Hayashida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7307326
    Abstract: A light receiving device includes a silicon substrate, a first P type diffusion layer on the silicon substrate, and a P type semiconductor layer on the P type diffusion layer. On a surface part of the P type semiconductor layer, two N type diffusion layers as light receiving parts, and a second P type diffusion layer between the two N type diffusion layers are provided. On the P type semiconductor layer, an antireflection film structure composed of a first silicon oxide formed by thermal oxidation and a second silicon oxide formed by CVD is provided. A film thickness of the first silicon oxide is set at about 15 nm, thus a defect in a interface between the first silicon oxide and the P type semiconductor layer is prevented. A film thickness of the second silicon oxide is set at about 100 nm, thus a leak current between cathodes is prevented when a power supply voltage is applied for long period of time.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: December 11, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigeki Hayashida, Tatsuya Morioka, Yoshihiko Tani, Isamu Ohkubo, Hideo Wada
  • Patent number: 7098489
    Abstract: A plurality of N-type diffusion layers are formed a specified distance apart on a P-type semiconductor layer. A P-type leak prevention layer formed between at least N-type diffusion layers prevents leaking between the diffusion layers. A dielectric film is formed in at least a light incident area on a P-type semiconductor layer including the diffusion layers and the leak prevention layer. Accordingly, provided are a split type light receiving element positively functioning as a split type light receiving element even when charge is accumulated in the dielectric film and having a uniform sensitivity throughout the entire area on a light receiving surface, and a circuit-built-in light receiving element and an optical disk device using the split type light receiving element.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: August 29, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tatsuya Morioka, Shigeki Hayashida, Yoshihiko Tani, Isamu Ohkubo
  • Publication number: 20050126627
    Abstract: A solar cell includes at least: a semiconductor substrate having a pn junction and a plurality of microscopic depressions formed in a light-receiving surface thereof; a front electrode formed on the light-receiving surface of the substrate; and a rear electrode formed on a rear surface of the substrate. The plurality of depressions each have a ratio of the maximum depth to the maximum diameter of 0.5 to 2.
    Type: Application
    Filed: November 17, 2004
    Publication date: June 16, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Shigeki Hayashida
  • Publication number: 20050116320
    Abstract: A light receiving device includes a silicon substrate, a first P type diffusion layer on the silicon substrate, and a P type semiconductor layer on the P type diffusion layer. On a surface part of the P type semiconductor layer, two N type diffusion layers as light receiving parts, and a second P type diffusion layer between the two N type diffusion layers are provided. On the P type semiconductor layer, an antireflection film structure composed of a first silicon oxide formed by thermal oxidation and a second silicon oxide formed by CVD is provided. A film thickness of the first silicon oxide is set at about 15 nm, thus a defect in a interface between the first silicon oxide and the P type semiconductor layer is prevented. A film thickness of the second silicon oxide is set at about 100 nm, thus a leak current between cathodes is prevented when a power supply voltage is applied for long period of time.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 2, 2005
    Inventors: Shigeki Hayashida, Tatsuya Morioka, Yoshihiko Tani, Isamu Ohkubo, Hideo Wada
  • Patent number: 6873025
    Abstract: A photodiode includes a first conductivity type semiconductor substrate or a first conductivity type semiconductor layer; a second conductivity type semiconductor layer provided on the first conductivity type semiconductor substrate or the first conductivity type semiconductor layer; an anti-reflection film provided on a surface of a portion of the second conductivity type semiconductor layer which is in a light receiving area; a first conductive layer provided in an area in the vicinity of the light receiving area; and a passivation layer provided on the first conductive layer. Light incident on the photodiode is detected by a junction of the one of the first conductivity type semiconductor substrate and the first conductivity type semiconductor layer, and the second conductivity type semiconductor layer. The area in the vicinity of the light receiving area includes a window area having an opening in the passivation layer for partially exposing the first conductive layer.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: March 29, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hideo Wada, Isamu Ohkubo, Kazuhiro Natsuaki, Naoki Fukunaga, Shigeki Hayashida
  • Publication number: 20050045979
    Abstract: A first P-type diffusion layer and a P-type semiconductor layer are provided on a silicon substrate, and two N-type diffusion layers are provided on a front surface of this P-type semiconductor layer to form two light receiving units. Three-layer translucent films, a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are disposed on the N-type diffusion layers and on the P-type semiconductor layer between the two diffusion layers. Holes produced during a production process and distributed and captured in two interfaces between the three-layer translucent films can reduce a field intensity in the vicinity of the surface of the P-type semiconductor layer to below a conventional level and an inversion of a conductive type to reduce a leak current between the light receiving units accordingly.
    Type: Application
    Filed: November 29, 2002
    Publication date: March 3, 2005
    Inventors: Tatsuya Morioka, Shigeki Hayashida, Yoshihiko Tani, Isamu Ohkubo, Hideo Wada
  • Publication number: 20050045962
    Abstract: A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
    Type: Application
    Filed: April 24, 2003
    Publication date: March 3, 2005
    Inventors: Hiroshi Iwata, Masayuki Nakano, Shigeki Hayashida, Seizou Kakimoto, Toshimasa Matsuoka
  • Publication number: 20050001231
    Abstract: A light receiving device includes a P type diffusion layer (101), a P type semiconductor layer (102), an N type diffusion layer (103) serving as a light receiving part, and a light transmitting film (104), all formed on a p type silicon substrate (100). The N type diffusion layer (103) has a thickness of 0.8 ?m to 1.0 ?m which is larger than an absorption length of incident light having wavelength of 400 nm, and such a concentration profile that a impurity concentration is not higher than 1E19 cm?3 on a surface and has a peak in a vicinity of the surface. Since recombination of carriers generated by the incident light is prevented in the vicinity of the surface of the N type diffusion layer (103), sensitivity of the light receiving device is enhanced and response speed is increased by the low-resistance N type diffusion layer (103) having a larger junction depth.
    Type: Application
    Filed: December 10, 2002
    Publication date: January 6, 2005
    Inventors: Shigeki Hayashida, Tatsuya Morioka, Yoshihiko Tani, Isamu Ohkubo, Hideo Wada
  • Publication number: 20040169247
    Abstract: A plurality of N-type diffusion layers (105, 108) are formed a specified distance apart on a P-type semiconductor layer (102). A P-type leak prevention layer (109) formed between at least N-type diffusion layers (105, 108) prevents leaking between the diffusion layers (105, 108). A dielectric film (115) is formed in at least a light incident area on a P-type semiconductor layer (102) including the diffusion layers (105, 108) and the leak prevention layer (109). Accordingly, provided are a split type light receiving element positively functioning as a split type light receiving element even when charge is accumulated in the dielectric film and having a uniform sensitivity throughout the entire area on a light receiving surface, and a circuit-built-in light receiving element and an optical disk device using the split type light receiving element.
    Type: Application
    Filed: January 12, 2004
    Publication date: September 2, 2004
    Inventors: Tatsuya Morioka, Shigeki Hayashida, Yoshihiko Tani, Isamu Ohkubo
  • Patent number: 6747316
    Abstract: A surface-channel MOS transistor comprising; a gate electrode formed on a semiconductor substrate with a gate dielectric film therebetween and source/drain regions formed in the semiconductor substrate wherein the gate electrode is formed at least a polysilicon layer of a thickness of 100 to 200 nm uniformly doped with an impurity and the source/drain regions contains the same impurity in self-alignment with the gate electrode.
    Type: Grant
    Filed: July 2, 1996
    Date of Patent: June 8, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshimasa Matsuoka, Seizou Kakimoto, Shigeki Hayashida, Hiroshi Iwata
  • Patent number: 6720627
    Abstract: A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: April 13, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Masayuki Nakano, Shigeki Hayashida, Seizou Kakimoto, Toshimasa Matsuoka
  • Patent number: 6580095
    Abstract: A circuit-containing photodetector is provided which can have a high sensitivity and response to light of a short wavelength and can be manufactured in a good yield. The circuit-containing photodetector includes a semiconductor substrate, a semiconductor layer formed thereon, and a conductive impurity region formed in the semiconductor layer for transmitting a signal. In the semiconductor layer, a trench is formed to have a depth to reach the substrate. An impurity region of a photodetector element is formed at the surface of the semiconductor substrate exposed at the bottom of the trench. A signal processing circuit for processing an electric signal from the photodetector element is formed on the semiconductor layer. The conductive impurity region for transmitting the electric signal from the photodetector element is formed to extend from the bottom of the trench to the upper surface of the semiconductor layer.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: June 17, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiko Tani, Shigeki Hayashida, Tatsuya Morioka, Seizo Kakimoto, Toshihiko Fukushima
  • Patent number: 6492702
    Abstract: A circuit-incorporating light receiving device comprises a first semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a diffusion region of the second conductivity type, provided in a first portion of the second semiconductor layer of the first conductivity type, a circuit element provided in the first portion of the first semiconductor layer of the first conductivity type and a second portion of the second semiconductor layer of the first conductivity type. The second semiconductor layer of the first conductivity type and the diffusion region of the second conductivity type form a light detection photodiode portion, and the diffusion region of the second conductivity type has a diffusion depth less than or equal to a penetration depth of short-wavelength signal light.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: December 10, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihiko Fukushima, Masaru Kubo, Shigeki Hayashida
  • Publication number: 20020047175
    Abstract: A circuit-containing photodetector is provided which can have a high sensitivity and response to light of a short wavelength and can be manufactured in a good yield. The circuit-containing photodetector includes a semiconductor substrate, a semiconductor layer formed thereon, and a conductive impurity region formed in the semiconductor layer for transmitting a signal. In the semiconductor layer, a trench is formed to have a depth to reach the substrate. An impurity region of a photodetector element is formed at the surface of the semiconductor substrate exposed at the bottom of the trench. A signal processing circuit for processing an electric signal from the photodetector element is formed on the semiconductor layer. The conductive impurity region for transmitting the electric signal from the photodetector element is formed to extend from the bottom of the trench to the upper surface of the semiconductor layer.
    Type: Application
    Filed: June 7, 2001
    Publication date: April 25, 2002
    Inventors: Yoshihiko Tani, Shigeki Hayashida, Tatsuya Morioka, Seizo Kakimoto, Toshihiko Fukushima
  • Publication number: 20020043689
    Abstract: A surface-channel MOS transistor comprising; a gate electrode formed on a semiconductor substrate with a gate dielectric film therebetween and source/drain regions formed in the semiconductor substrate wherein the gate electrode is formed at least a polysilicon layer of a thickness of 100 to 200 nm uniformly doped with an impurity and the source/drain regions contains the same impurity in self-alignment with the gate electrode.
    Type: Application
    Filed: July 2, 1996
    Publication date: April 18, 2002
    Inventors: TOSHIMASA MATSUOKA, SEIZOU KAKIMOTO, SHIGEKI HAYASHIDA, HIROSHI IWATA
  • Publication number: 20020038868
    Abstract: A photodiode includes a first conductivity type semiconductor substrate or a first conductivity type semiconductor layer; a second conductivity type semiconductor layer provided on the first conductivity type semiconductor substrate or the first conductivity type semiconductor layer; an anti-reflection film provided on a surface of a portion of the second conductivity type semiconductor layer which is in a light receiving area; a first conductive layer provided in an area in the vicinity of the light receiving area; and a passivation layer provided on the first conductive layer. Light incident on the photodiode is detected by a junction of the one of the first conductivity type semiconductor substrate and the first conductivity type semiconductor layer, and the second conductivity type semiconductor layer. The area in the vicinity of the light receiving area includes a window area having an opening in the passivation layer for partially exposing the first conductive layer.
    Type: Application
    Filed: October 30, 2001
    Publication date: April 4, 2002
    Inventors: Hideo Wada, Isamu Ohkubo, Kazuhiro Natsuaki, Naoki Fukunaga, Shigeki Hayashida
  • Publication number: 20010038096
    Abstract: A circuit-incorporating light receiving device comprises a first semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a diffusion region of the second conductivity type, provided in a first portion of the second semiconductor layer of the first conductivity type, a circuit element provided in the first portion of the first semiconductor layer of the first conductivity type and a second portion of the second semiconductor layer of the first conductivity type. The second semiconductor layer of the first conductivity type and the diffusion region of the second conductivity type form a light detection photodiode portion, and the diffusion region of the second conductivity type has a diffusion depth less than or equal to a penetration depth of short-wavelength signal light.
    Type: Application
    Filed: March 29, 2001
    Publication date: November 8, 2001
    Inventors: Toshihiko Fukushima, Masaru Kubo, Shigeki Hayashida
  • Patent number: 6255702
    Abstract: A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: July 3, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Masayuki Nakano, Shigeki Hayashida, Seizou Kakimoto, Toshimasa Matsuoka
  • Patent number: 5960319
    Abstract: A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: September 28, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Masayuki Nakano, Shigeki Hayashida, Seizou Kakimoto, Toshimasa Matsuoka
  • Patent number: 5903029
    Abstract: An insulated-gate field-effect transistor formed in a substrate of a first conductive type or in a well of the first conductive type formed in the substrate is provided. The transistor includes a channel region containing an impurity of the first conductive type; and a source-drain region containing an impurity of a second conductive type. The source-drain region further contains an impurity of the first conductive type; and a concentration of the impurity of the first conductive type contained in the source-drain region is greater than a concentration of the impurity of the first conductive type contained in the channel region but is less than a concentration of the impurity of the second conductive type contained in the source-drain region.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: May 11, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigeki Hayashida, Seizo Kakimoto