Abstract: A video recording apparatus wherein in the case where video recording programming information generated by an automatic video recording programming control unit is already present in a video recording programming information table, the video recording programming information is recorded in duplicated video recording information table. In the case where other video recording apparatuses connected via network cancelled the video recording programming information, which had been registered in the duplicated video recording information table, a video recording programming control unit stores the video recording programming information in a video recording programming table, and a video recording control unit executes video recording, based on the video recording programming information table.

Abstract: A digest image preparation apparatus includes an image coding circuit for receiving a moving picture to output a coded image obtained by coding the moving picture and extracting a certaing feature parameters produced upon the coding to be outputted, a feature vector computation circuit for receiving the feature parameters to output feature vectors of image frames defined in n dimensions and a curve simplification circuit for simplifying loci generated by arranging the n-dimensional feature vectors outputted by the feature vector computation circuit in time series manner to output ranking information. It then becomes possible to reduce a necessary cost for the image coding and a ranking information calculation.

Abstract: A digest image preparation apparatus includes an image coding circuit for receiving a moving picture to output a coded image obtained by coding the moving picture and extracting a certaing feature parameters produced upon the coding to be outputted, a feature vector computation circuit for receiving the feature parameters to output feature vectors of image frames defined in n dimensions and a curve simplification circuit for simplifying loci generated by arranging the n-dimensional feature vectors outputted by the feature vector computation circuit in time series manner to output ranking information. It then becomes possible to reduce a necessary cost for the image coding and a ranking information calculation.

Abstract: In a system in which a CPU 2 and a motion compensation coprocessor 1 are interconnected via a bus 3, the motion compensation coprocessor 1 has computation descriptor registers 12 that are chainable on an individual process basis, and comprises means for reading reference data in accordance with the contents of the computation descriptor registers, means for outputting a computation result, a read/storage circuit 18 for storing reference data, a write/storage circuit 19 for storing a computation result, and a motion compensation computing unit 17.