Patents by Inventor Shigeki Katou

Shigeki Katou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818682
    Abstract: To provide, in an increased production yield, a reliability-improved semiconductor product having both a planar type transistor and a fin type transistor. A semiconductor device having both a planar type transistor and a fin type transistor is manufactured by decreasing the thickness of a hard mask for the formation of element isolation in the planar type transistor region prior to formation of element isolation in the fin type transistor region.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 27, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shigeki Katou
  • Patent number: 10546865
    Abstract: The reliability of a semiconductor device is improved. A control gate electrode and a memory gate electrode for memory cell of a nonvolatile memory, a first gate electrode and a dummy gate electrode for peripheral circuit are formed. Then, a first insulation film is formed so as to cover them. The gate length of the first gate electrode is larger than the gate length of the control gate electrode. Then, an opening is formed in the first insulation film, to etch and reduce the height of the first gate electrode exposed from the opening. Thereafter, over the first insulation film, an insulation film is formed. Then, the insulation film is polished, to expose the control gate electrode, the memory gate electrode, the first gate electrode, and the dummy gate electrode. Then, the dummy gate electrode is removed. A gate electrode is formed in the removal region.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shigeki Katou
  • Publication number: 20190312048
    Abstract: To provide, in an increased production yield, a reliability-improved semiconductor product having both a planar type transistor and a fin type transistor. A semiconductor device having both a planar type transistor and a fin type transistor is manufactured by decreasing the thickness of a hard mask for the formation of element isolation in the planar type transistor region prior to formation of element isolation in the fin type transistor region.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 10, 2019
    Inventor: Shigeki KATOU
  • Publication number: 20180204847
    Abstract: The reliability of a semiconductor device is improved. A control gate electrode and a memory gate electrode for memory cell of a nonvolatile memory, a first gate electrode and a dummy gate electrode for peripheral circuit are formed. Then, a first insulation film is formed so as to cover them. The gate length of the first gate electrode is larger than the gate length of the control gate electrode. Then, an opening is formed in the first insulation film, to etch and reduce the height of the first gate electrode exposed from the opening. Thereafter, over the first insulation film, an insulation film is formed. Then, the insulation film is polished, to expose the control gate electrode, the memory gate electrode, the first gate electrode, and the dummy gate electrode. Then, the dummy gate electrode is removed. A gate electrode is formed in the removal region.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 19, 2018
    Inventor: Shigeki KATOU
  • Publication number: 20170229562
    Abstract: When forming a MISFET by replacing a dummy gate electrode with a metal gate electrode in a gate last process, formation caused by polishing of an interlayer insulation film of a silicide layer over an upper surface of the dummy gate electrode to result in hampering the removal of the dummy gate is prevented. In the gate last process, when an interlayer insulation film is polished to expose an upper surface of a dummy gate electrode, a slurry mixed with an acidic aqueous solution is used to prevent silicide layer formation over the upper surface of the dummy gate electrode.
    Type: Application
    Filed: January 19, 2017
    Publication date: August 10, 2017
    Applicant: Renesas Electronics Corporation
    Inventor: Shigeki KATOU
  • Patent number: 7943334
    Abstract: The present invention provides an immunological detection method that can detect milk allergens, allergens of albumen, flour, buckwheat and peanut with high sensitivity in foods containing these allergens regardless they are denatured/native, and a detection kit to be used therefor. It is a method for detecting allergens by using 2 or more monoclonal antibodies recognizing native and denatured milk allergens, native and denatured albumen allergens, native and denatured flour allergens, native and denatured buckwheat allergens, and native and denatured peanut allergens, using asl casein which is the main protein of milk casein, ?-lactoglobulin which is the main protein of whey, ovalubumin and ovomucoid which are main proteins of albumen, gliadin which is the main protein of flour, protein with a molecular weight of 24 kDa and 76 kDa which are main proteins of buckwheat, and Ara h1 which is the main protein of peanut as an index.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: May 17, 2011
    Assignee: Prima Meat Packers, Ltd.
    Inventors: Masanobu Akimoto, Shigeki Katou, Makoto Namioka
  • Patent number: 7574228
    Abstract: Stored in an each speaker's sound volume coefficient table 13 are a speaker identification ID and information of a voice coefficient so as to be correlated with each other. A speaker identification unit 11 extracts an each speaker's ID from a received packet based on floor control information or outputs the packet as an RTP packet to an RTP buffer. A sound volume control unit 12 executes a control program 14a of a recording medium 14 to record a current speaker identification ID and reads a sound volume coefficient relevant to the speaker identification ID from the each speaker's sound volume coefficient table 13 to output the coefficient as sound volume control information. In this case, the sound volume control unit 12 increments/decrements the relevant sound volume coefficient based on sound volume adjustment information of a sound volume adjustment unit.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: August 11, 2009
    Assignee: NEC Corporation
    Inventor: Shigeki Katou
  • Publication number: 20070275427
    Abstract: The present invention provides an immunological detection method that can detect milk allergens, allergens of albumen, flour, buckwheat and peanut with high sensitivity in foods containing these allergens regardless they are denatured/native, and a detection kit to be used therefor. It is a method for detecting allergens by using 2 or more monoclonal antibodies recognizing native and denatured milk allergens, native and denatured albumen allergens, native and denatured flour allergens, native and denatured buckwheat allergens, and native and denatured peanut allergens, using asl casein which is the main protein of milk casein, ?-lactoglobulin which is the main protein of whey, ovalubumin and ovomucoid which are main proteins of albumen, gliadin which is the main protein of flour, protein with a molecular weight of 24 kDa and 76 kDa which are main proteins of buckwheat, and Ara h1 which is the main protein of peanut as an index.
    Type: Application
    Filed: March 4, 2005
    Publication date: November 29, 2007
    Applicant: PRIMA MEAT PACKER, LTD
    Inventors: Masanobu Akimoto, Shigeki Katou, Makoto Namioka
  • Publication number: 20060098591
    Abstract: Stored in an each speaker's sound volume coefficient table 13 are a speaker identification ID and information of a voice coefficient so as to be correlated with each other. A speaker identification unit 11 extracts an each speaker's ID from a received packet based on floor control information or outputs the packet as an RTP packet to an RTP buffer. A sound volume control unit 12 executes a control program 14a of a recording medium 14 to record a current speaker identification ID and reads a sound volume coefficient relevant to the speaker identification ID from the each speaker's sound volume coefficient table 13 to output the coefficient as sound volume control information. In this case, the sound volume control unit 12 increments/decrements the relevant sound volume coefficient based on sound volume adjustment information of a sound volume adjustment unit.
    Type: Application
    Filed: November 3, 2005
    Publication date: May 11, 2006
    Inventor: Shigeki Katou
  • Patent number: 5712640
    Abstract: A FM radar alarm system for use on a motor vehicle detects a following motor vehicle in an adjacent lane behind the motor vehicle. The FM radar alarm system includes an FM radar module including a near-region monitoring antenna and a far-region monitoring antenna. The near-region monitoring antenna radiates a relatively wide radio-wave beam in a near region positioned behind the motor vehicle and extending over an adjacent lane. The far-region monitoring antenna radiates a relatively narrow radio-wave beam in a far region positioned behind the motor vehicle and extending over the adjacent lane.
    Type: Grant
    Filed: November 27, 1995
    Date of Patent: January 27, 1998
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Hiroyuki Andou, Shigeki Katou