Abstract: Disclosed is a video signal output circuit including: a clamp circuit; a first differential amplifying circuit; a dividing circuit; and an offset circuit which adds or subtracts a predetermined offset voltage to or from a bias voltage, a reference voltage, or a base reference voltage generated by the dividing circuit so as to supply an offset voltage added/subtracted voltage to the clamp circuit or the first differential amplifying circuit, wherein the offset circuit includes a pnp bipolar transistor and an npn bipolar transistor, and outputs a difference voltage corresponding to a difference between a base-emitter voltage of the pnp bipolar transistor and a base-emitter voltage of the npn bipolar transistor.

Abstract: Disclosed is a video signal output circuit including: a clamp circuit; a first differential amplifying circuit; a dividing circuit; and an offset circuit which adds or subtracts a predetermined offset voltage to or from a bias voltage, a reference voltage, or a base reference voltage generated by the dividing circuit so as to supply an offset voltage added/subtracted voltage to the clamp circuit or the first differential amplifying circuit, wherein the offset circuit includes a pnp bipolar transistor and an npn bipolar transistor, and outputs a difference voltage corresponding to a difference between a base-emitter voltage of the pnp bipolar transistor and a base-emitter voltage of the npn bipolar transistor.

Abstract: An image signal input circuit includes an input terminal configured to receive an image signal, a clamp circuit configured to hold a sink chip voltage contained in the image signal to be a constant value, a level shift circuit that includes a first emitter follower having a first transistor and a first current source, and a second emitter follower having a second transistor and a second current source, a base of the second transistor being connected to an emitter of the first transistor, and that is configured to shift a level of the sink chip voltage which is held constant, and an electric current source configured to attract a base current of the first transistor.

Abstract: An image signal input circuit includes an input terminal configured to receive an image signal, a clamp circuit configured to hold a sink chip voltage contained in the image signal to be a constant value, a level shift circuit that includes a first emitter follower having a first transistor and a first current source, and a second emitter follower having a second transistor and a second current source, a base of the second transistor being connected to an emitter of the first transistor, and that is configured to shift a level of the sink chip voltage which is held constant, and an electric current source configured to attract a base current of the first transistor.

Abstract: A variable gain amplifier circuit capable of eliminating circuit elements and the area for circuits when formed into an integrated circuit is disclosed. The circuit includes plural differential circuits, one of the input terminals of each of the differential circuits being connected in common to a signal input terminal, any one of the differential circuits being selected to operate; an output circuit having an input terminal connected in common to each output terminal of the differential circuits, the output circuit inputting an output signal of any of differential circuits and outputting an output signal from the signal output terminal; and plural resistors connected in series between the signal output terminal and a reference voltage terminal, in which each of junctions between the resistors is connected to one of the other input terminals of the differential circuits.

Abstract: A variable-gain amplifier circuit capable of eliminating circuit elements and the area for circuits when formed into an integrated circuit is disclosed. The circuit includes plural differential circuits, one of the input terminals of each of the differential circuits being connected in common to a signal input terminal, any one of the differential circuits being selected to operate; an output circuit having an input terminal connected in common to each output terminal of the differential circuits, the output circuit inputting an output signal of any of differential circuits and outputting an output signal from the signal output terminal; and plural resistors connected in series between the signal output terminal and a reference voltage terminal, in which each of junctions between the resistors is connected to one of the other input terminals of the differential circuits.

Abstract: A technology for promoting distribution of IPs which constitute part of an integrated circuit is provided. An LSI maker concludes a contract for business alliance with an IP provider, acquires data on IPs from the IP provider, conducts layout, wiring, and verification of the acquired IPs, registers verified IPs into a library, and presents the same to a set maker. When the set maker orders for manufacturing of an LSI to the LSI maker, the LSI maker designs the logic of the integrated circuit, conducts layout, wiring, and timing simulation, and have evaluations from the set maker. Then, the LSI maker manufactures LSIs, delivers the same to the set maker, and receives the payment. The LSI maker calculates license fees, and pays them to the IP provider.

Abstract: A technology for promoting distribution of IPs which constitute part of an integrated circuit is provided. An LSI maker concludes a contract for business alliance with an IP provider, acquires data on IPs from the IP provider, conducts layout, wiring, and verification of the acquired IPs, registers verified IPs into a library, and presents the same to a set maker. When the set maker orders for manufacturing of an LSI to the LSI maker, the LSI maker designs the logic of the integrated circuit, conducts layout, wiring, and timing simulation, and have evaluations from the set maker. Then, the LSI maker manufactures LSIs, delivers the same to the set maker, and receives the payment. The LSI maker calculates license fees, and pays them to the IP provider.

Abstract: A main function unit is an IP that implements by hardware main functions selected from a group of functions provided by an integrated circuit. A sub-function unit implements by software some of the group of functions provided by the integrated circuit. A process managing unit responds to an external signal and directs at least the sub-function unit to perform a process.