Abstract: An active pull-up circuit for use in a sense amplifier or the like, comprises an enhancement type MIS transistor, a MIS capacitor controlled by a clock signal, and a depletion type MIS transistor controlled by another clock signal (.phi..sub.2 '). In this circuit, the two clock signals are bilevel signals having potentials which are the same as potentials of two power supplies.

Abstract: Disclosed is a dynamic semiconductor memory device with decreased clocks having a pull up circuit associated with a pair of bit lines. The pull up circuit comprises a pair of first switching transistors connected between a power supply line and the associated bit line, and, a pair of second switching transistors. Each gate of the second switching transistors is connected to the bit line of opposite side. The turning on or off of the second switching transistor controls the gate potential of the first switching transistor.

Abstract: A semiconductor memory testing device and testing method comprises an address pattern generator which successively generates an address pattern which specifies the X-Y addresses of each memory cell of a semiconductor memory device which is to be tested, an address changeover or swapping device which makes access to the semiconductor memory device with the address pattern supplied by the address pattern generator during normal operation mode, and addresses interchanged during swap operation mode, a comparator which compares data from the semiconductor memory device with an expected value to detect hardware error, and a fail memory device which stores information concerning the existence hardware error in each of the memory cells of the semiconductor memory device in an address region corresponding to that of the bad cell of the semiconductor memory device. The semiconductor memory device and the fail memory device both receive common X-Y addresses from the address changeover or swapping device.