Abstract: A resistance dividing circuit includes a resistive element formed in an area in a first line segment and a second line segment which are set on a substrate and arranged in parallel to each other; and a tap portion connected to the resistive element at a predetermined position of the first line side. A cutout in which the resistive element does not exist is formed in a place corresponding to the predetermined position in a lengthwise direction of the resistive element. In such a structure, a deviation of an actually generated divided voltage from a design value thereof can be reduced so that a highly correct gray-scale display can be achieved.

Abstract: In a data line driver for driving data lines of a display apparatus, a data register is adapted to latch video data and a definite non-video gradation data via a data bus. A data latch circuit is adapted to latch the video data and the definite non-video gradation data at different timings to generate digital output signals. A digital/analog converter is adapted to convert the digital output signals of the data latch circuit into analog signals. An output buffer is adapted to apply the analog signals of the digital/analog converter to the data lines.

Abstract: A voltage selection unit selects, based on a grayscale value represented by e.g. 10-bit grayscale data D<9:0>, two voltages Vb1 and Vb2 from among ?-correction voltages Va0, Va1, Va16, . . . , Va1008, Va1022, and Va1023 generated from one reference voltage. A divided voltage generation unit generates divided voltages Vc1-Vc16 by dividing a voltage difference between the Vb1 and Vb2 into 16 equal parts. The divided voltage generation unit makes a voltage value of the Vc1 that of the Va0 when the Va0 is selected, makes a voltage value of the Vc2 that of the Va1 when the Va1 is selected, makes a voltage value of the Vc15 that of the Va1022 when the Va1022 is selected, and makes a voltage value of the Vc16 that of the Va1023 when the Va1023 is selected. A DAC selects one divided voltage from among the Vc1-Vc16 based on lower-order four bits D<3:0>.

Abstract: A driver of a display device has an output buffer, a frame control circuit outputting a frame switch signal with respect to each frame, and an offset compensation control circuit outputting an offset compensation control signal to the output buffer in response to the frame switch signal. One frame includes a display period and a non-display period. In normal processing, the frame control circuit receives a first vertical synchronizing in one frame and outputs the frame switch signal from the receipt of the first vertical synchronizing signal to before the non-display period within the same frame. In special processing, the frame control circuit further receives a second vertical synchronizing signal in the non-display period in one frame, and further outputs the frame switch signal for a time from the receipt of the second vertical synchronizing signal to before the non-display period in the next frame.

Abstract: A resistance dividing circuit includes a resistive element formed in an area in a first line segment and a second line segment which are set on a substrate and arranged in parallel to each other; and a tap portion connected to the resistive element at a predetermined position of the first line side. A cutout in which the resistive element does not exist is formed in a place corresponding to the predetermined position in a lengthwise direction of the resistive element. In such a structure, a deviation of an actually generated divided voltage from a design value thereof can be reduced so that a highly correct gray-scale display can be achieved.

Abstract: In a data line driver for driving data lines of a display apparatus including a data register adapted to sequentially latch video data signals in synchronization with latch signals, a data latch circuit adapted to latch all the sequential video data signals latched in the data register in synchronization with a strobe signal to generate digital output signals, a digital/analog converter adapted to convert the digital output signals of the data latch circuit into analog signals, and an output buffer adapted to apply the analog signals of the digital/analog converter to the data lines, the data latch circuit has a reset terminal adapted to receive a reset signal, so that the digital output signals of the data latch circuit are reset by the reset signal to fixed gradation data regardless of the strobe signal.

Abstract: In a data line driver for driving data lines of a display apparatus, a data register is adapted to latch video data and a definite non-video gradation data via a data bus. A data latch circuit is adapted to latch the video data and the definite non-video gradation data at different timings to generate digital output signals. A digital/analog converter is adapted to convert the digital output signals of the data latch circuit into analog signals. An output buffer is adapted to apply the analog signals of the digital/analog converter to the data lines.

Abstract: In a data line driver for driving data lines of a display apparatus including a data register adapted to sequentially latch video data signals in synchronization with latch signals, a data latch circuit adapted to latch all the sequential video data signals latched in the data register in synchronization with a strobe signal to generate digital output signals, a digital/analog converter adapted to convert the digital output signals of the data latch circuit into analog signals, and an output buffer adapted to apply the analog signals of the digital/analog converter to the data lines, the data latch circuit has a reset terminal adapted to receive a reset signal, so that the digital output signals of the data latch circuit are reset by the reset signal to fixed gradation data regardless of the strobe signal.

Abstract: A halftone-level reference voltage is generated by a resistance-type potential divider circuit from a potential between a high-potential grayscale voltage and a low-potential grayscale voltage on the side of positive polarity, and a halftone-level grayscale voltage, which is capable of being varied, is generated from the halftone reference voltage by an amplifier, which uses a variable resistor as a feedback resistor. All grayscale voltages on the side of positive polarity are inverted with respect to the ground potential of a liquid crystal panel and amplified by the same ratio by amplifiers. As a result, grayscale voltages on the side of negative polarity are produced as outputs. Potentials to which feed-through correction values have been added are set individually as liquid crystal ground potentials on low- and high-potential sides. With regard to halftone levels, feed-through correction values are adjusted automatically in conformity with amount of change in grayscale voltage.

Abstract: An active matrix liquid display system where two scanning lines are successively selected within one horizontal scanning period, by which display voltages are written on pixels lined up in a horizontal direction, and the voltage supplied to a signal line when an even number display pixel is selected and the voltage supplied to a signal line when an odd number display pixel is selected are switched according to a gradation voltage generated from a gradation power source. Accordingly, when there is implemented a dot inversion drive in the active matrix liquid display system where there are less number of signal line drive circuits, and when a former stage pixel is subjected to modulation due to interpixel parasitic capacitance, it is possible to equalize an electric voltage of the former stage pixel being modulated as a latter stage pixel is being written with an electric voltage of the latter stage pixel, owing to revision of a gradation voltage of the former stage pixel.