Patents by Inventor Shigeki Onodera

Shigeki Onodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6734075
    Abstract: A CMOS device includes a reverse electric conduction type well (2) formed on a monoelectric conduction type semiconductor substrate (1), a first MOS transistor (3) of a reverse electric conduction type channel formed on a surface of the semiconductor substrate, and a second MOS transistor (4) of monoelectric conduction type channel is formed on a surface of the well. In the present invention, resistance elements (8R, 7R, 2R) are formed in the semiconductor substrate on a lower side of a thick field oxide film (9) covering a surface of the semiconductor substrate. Further, a second resistance element (11R) composed of a polycrystal silicon layer is formed on an upper side of the field oxide film.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: May 11, 2004
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Shigeki Onodera
  • Patent number: 6479338
    Abstract: A semiconductor substrate having a first conductivity type is first prepared. Then, a well region is formed in the substrate so as to have a second conductivity type opposite to the first conductivity type. Next, a first ion having the first conductivity type is implanted into the well region to form a region to be a first drain region having a first impurity density and into the substrate to form a region to be a first channel stopper region. Next, a second ion having the second conductivity type is implanted into the well to form a region to be a second channel stopper region and into the substrate to form a region to be a the second drain region having a second impurity density. Then, the respective ion implanted regions are thermally diffused to form the first drain region and the second channel stopper region in the well region and to form the second drain region and the first channel stopper region in the substrate.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: November 12, 2002
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Shigeki Onodera, Ichiro Ohashi
  • Publication number: 20020072169
    Abstract: A semiconductor substrate having a first conductivity type is first prepared. Then, a well region is formed in the substrate so as to have a second conductivity type opposite to the first conductivity type. Next, a first ion having the first conductivity type is implanted into the well region to form a region to be a first drain region having a first impurity density and into the substrate to form a region to be a first channel stopper region. Next, a second ion having the second conductivity type is implanted into the well to form a region to be a second channel stopper region and into the substrate to form a region to be a the second drain region having a second impurity density. Then, the respective ion implanted regions are thermally diffused to form the first drain region and the second channel stopper region in the well region and to form the second drain region and the first channel stopper region in the substrate.
    Type: Application
    Filed: November 29, 2000
    Publication date: June 13, 2002
    Inventors: Shigeki Onodera, Ichiro Ohashi
  • Publication number: 20020064925
    Abstract: A semiconductor substrate having a first conductivity type is first prepared. Then, a well region is formed in the substrate so as to have a second conductivity type opposite to the first conductivity type. Next, a first ion having the first conductivity type is implanted into the well region to form a region to be a first drain region having a first impurity density and into the substrate to form a region to be a first channel stopper region. Next, a second ion having the second conductivity type is implanted into the well to form a region to be a second channel stopper region and into the substrate to form a region to be a the second drain region having a second impurity density. Then, the respective ion implanted regions are thermally diffused to form the first drain region and the second channel stopper region in the well region and to form the second drain region and the first channel stopper region in the substrate.
    Type: Application
    Filed: November 30, 2001
    Publication date: May 30, 2002
    Inventors: Shigeki Onodera, Ichiro Ohashi
  • Publication number: 20010049171
    Abstract: A CMOS device includes a reverse electric conduction type well (2) is formed on a monoelectric conduction type semiconductor substrate (1), a first MOS transistor (3) of a reverse electric conduction type channel is formed on a surface of the semiconductor substrate, and a second MOS transistor (4) of monoelectric conduction type channel is formed on a surface of the well. In the present invention, resistance elements (8R, 7R, 2R) are formed in the semiconductor substrate on a lower side of a thick field oxide film (9) covering a surface of the semiconductor substrate. Further, a second resistance element (11R) composed of a polycrystal silicon layer is formed on an upper side of the field oxide film.
    Type: Application
    Filed: May 19, 1999
    Publication date: December 6, 2001
    Inventor: SHIGEKI ONODERA