Patents by Inventor Shigeki Tanaka

Shigeki Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9146481
    Abstract: A local exposure apparatus for performing exposure processing on a specific area of a photosensitive film formed on a substrate includes a substrate conveyor configured to define a substrate conveying path and to horizontally convey the substrate along the substrate conveying path, a chamber configured to define an exposure processing space, a light source including a plurality of light-emitting elements linearly arranged above the substrate conveying path, a light emission drive unit configured to selectively drive one or more of the light-emitting elements of the light source, a substrate detector configured to detect the substrate conveyed by the substrate conveyor, and a control unit configured to control the light emission drive unit such that, when the specific area of the photosensitive film moves below the light source, only the light-emitting elements capable of irradiating the given area are driven to emit the light.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 29, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshiharu Ota, Shigeru Moriyama, Yuki Matsumura, Shigeki Tanaka
  • Patent number: 9099484
    Abstract: A method of manufacturing a semiconductor device, includes providing a lead frame including a frame portion, including a through hole penetrating the lead frame, a device forming portion surrounded by the frame portion in plan view, including a die pad, and a semiconductor chip mounted on the die pad; after the providing step, sealing the semiconductor chip with sealing resin by supplying the sealing resin to the device forming portion via a first region of the frame portion in which the through hole is formed in plan view, thereby forming a sealing body sealing the device forming portion and the first region of the frame portion; and after the sealing step, removing a first part of the sealing body located at the first region of the frame portion from the lead frame by inserting a pin into the through hole.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: August 4, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Fujii, Shigeki Tanaka, Kazuaki Yoshida
  • Publication number: 20150211464
    Abstract: A fuel gas injection valve according to the present invention includes: a holder including a first injection hole through which fuel gas is injected to produce premixed fuel, and a second injection hole through which fuel gas is injected to produce diffusion fuel; a first needle valve that slidably reciprocates in the holder along an axial direction to open and close the first injection hole and the second injection hole; and a second needle valve having a sealing face on the top thereof and a through-hole provided along the axial direction at the central portion in a radial direction of the second needle valve, the sealing face being brought into contact with a needle valve seat provided in the holder, the first needle valve being slidably inserted into the through-hole, and the second needle valve reciprocating in the holder along the axial direction to prevent fuel gas from circulating to the first injection hole and the second injection hole when the sealing face is in contact with the needle valve seat,
    Type: Application
    Filed: August 15, 2013
    Publication date: July 30, 2015
    Inventors: Hiroyuki Ishida, Akihiro Miyanagi, Naohiro Hiraoka, Shigeki Tanaka, Sota Watanabe, Yasuyuki Komada
  • Publication number: 20150179480
    Abstract: A method of manufacturing a semiconductor device, includes providing a lead frame including a frame portion, including a through hole penetrating the lead frame, a device forming portion surrounded by the frame portion in plan view, including a die pad, and a semiconductor chip mounted on the die pad; after the providing step, sealing the semiconductor chip with sealing resin by supplying the sealing resin to the device forming portion via a first region of the frame portion in which the through hole is formed in plan view, thereby forming a sealing body sealing the device forming portion and the first region of the frame portion; and after the sealing step, removing a first part of the sealing body located at the first region of the frame portion from the lead frame by inserting a pin into the through hole.
    Type: Application
    Filed: February 27, 2015
    Publication date: June 25, 2015
    Inventors: Hiroshi Fujii, Shigeki Tanaka, Kazuaki Yoshida
  • Patent number: 8999761
    Abstract: To stably remove a resin body formed in a supply route of a resin in a sealing step. A leadframe has, in a sub-runner portion thereof, a sub-through-hole. The sub-through-hole has, along a first direction along which the sub-runner portion extends, a first portion located on the side of a main-runner portion and a second portion located on the side of a gate portion relative to the first portion. In a plan view, an opening width of the sub-through-hole in the first direction is greater than that of the sub-through-hole in a second direction perpendicular to the first direction. In a plan view, an opening width of the sub-through-hole in the second direction gradually decreases from the first portion to an end portion of the second portion on the side of the gate portion.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Fujii, Shigeki Tanaka, Kazuaki Yoshida
  • Publication number: 20140349447
    Abstract: To stably remove a resin body formed in a supply route of a resin in a sealing step. A leadframe has, in a sub-runner portion thereof, a sub-through-hole. The sub-through-hole has, along a first direction along which the sub-runner portion extends, a first portion located on the side of a main-runner portion and a second portion located on the side of a gate portion relative to the first portion. In a plan view, an opening width of the sub-through-hole in the first direction is greater than that of the sub-through-hole in a second direction perpendicular to the first direction. In a plan view, an opening width of the sub-through-hole in the second direction gradually decreases from the first portion to an end portion of the second portion on the side of the gate portion.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 27, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroshi Fujii, Shigeki Tanaka, Kazuaki Yoshida
  • Publication number: 20130235278
    Abstract: A method of manufacturing a liquid crystal panel in which the bright point defect is effectively corrected is provided. The method of manufacturing a liquid crystal panel 11 including a pair of substrates 40 and 30, and a liquid crystal layer 50 provided between the pair of the substrates 40 and 30 includes detecting a bright point defect in the liquid crystal panel 11; forming a first light blocking portion BL1 in one of the substrates 40 and 30 and in a part of an area that surrounds the bright point defect with a plan view; forming a recess in a portion of one of the substrates 40, 30 that overlaps the bright point defect and on a surface of the one of the substrates 40 and 30 that is opposite from a surface facing the liquid crystal layer; and forming a second light blocking portion BL2 in the recess.
    Type: Application
    Filed: October 7, 2011
    Publication date: September 12, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shigeki Tanaka, Nobufumi Tomimaru, Makoto Kanbe, Shunichi Takeuchi, Taimi Oketani
  • Patent number: 8466540
    Abstract: The reliability of a semiconductor device is prevented from being reduced. A planar shape of a sealing body is comprised of a quadrangle having a pair of first sides, and a pair of second sides crossing with the first sides. Further, it has a die pad, a controller chip (first semiconductor chip) and a sensor chip (second semiconductor chip) mounted over the die pad, and a plurality of leads arranged along the first sides of the sealing body. The controller chip and the leads are electrically coupled to each other via wires (first wires), and the sensor chip and the controller chip are electrically coupled to each other via wires (second wires). Herein, the die pad is supported by a plurality of suspending leads formed integrally with the die pad and extending from the die pad toward the first sides of the sealing body. Each of the suspending leads has an offset part.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: June 18, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeki Tanaka, Masakazu Sakano, Toshiyuki Shinya, Takafumi Konno, Kazuaki Yoshida, Takashi Sato, Atsushi Fujisawa
  • Patent number: 8399302
    Abstract: The occurrence of a resin seal failure is suppressed. A molding step is carried out using a lead frame in which there are formed multiple air vent portions for discharging gas in each cavity formed in the upper die of a molding die to outside the cavity. The air vent portions are formed at positions overlapping with the other corner portions, arranged inside a gate portion of the cavity. Each of the air vent portions is led out from the other corner portions of the cavity to outside a clamp area and is extended along sides of the cavity, respectively, in the clamp area.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: March 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeki Tanaka, Atsushi Fujisawa, Masahiro Tani, Satoru Suzuki
  • Publication number: 20120307187
    Abstract: A method for producing a liquid crystal display panel (1) including a pair of transparent substrates (3, 4) opposed to each other, a liquid crystal layer (2) that contains liquid crystal molecules (21) and is sandwiched between the substrates, and optical alignment films (36, 46) for aligning the liquid crystal molecules, the films being formed on inner surfaces of the substrates and subjected to an alignment treatment through light irradiation, includes the step of bonding the substrates to each other while sandwiching the layer therebetween, where the optical alignment films that are yet to be subjected to the treatment are each formed on the substrates, and the step of subjecting the optical alignment films to the treatment where the light (51) is projected from an outer surface of either one of the bonded substrates toward an outer surface of the other substrate to obliquely traverse the optical alignment films.
    Type: Application
    Filed: December 6, 2010
    Publication date: December 6, 2012
    Inventor: Shigeki Tanaka
  • Patent number: 8300202
    Abstract: A liquid crystal display panel (50a) includes a pair of substrates arranged, facing each other, a liquid crystal layer provided between the pair of substrates, and a frame-like sealing member (25) configured to bond the pair of substrates with each other and enclose the liquid crystal layer. A cavity forming wall (18ba) is provided on one of the pair of substrates between the liquid crystal layer and the sealing member (25) and is configured to form a cavity region (C) therein by an upper end of the cavity forming wall contacting the other of the pair of substrates. The cavity region (C) is configured so that, when an excessive amount of a liquid crystal material which foims the liquid crystal layer is enclosed, the cavity forming wall is destroyed to cause a portion of the liquid crystal material to flow into the cavity region (C).
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: October 30, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Shigeki Tanaka
  • Patent number: 8193041
    Abstract: The yield of a semiconductor device is improved. Inside the resin sealing body which forms a semiconductor device, the semiconductor chip is sealed in the state where it has arranged aslant to the upper and lower sides of a resin sealing body. In the suspension lead which supports the die pad carrying this semiconductor chip, the small recess is formed in the fifth surface of the opposite side with the surface on which the semiconductor chip was mounted. This recess is a portion used as the starting point when making die pad 2a slanting. The side surface of the side near a die pad between two side surfaces of this recess is formed in the state where it inclined rather than the side surface of the side near the periphery of a resin sealing body.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Shigeki Tanaka
  • Publication number: 20120092574
    Abstract: Provided is a liquid crystal display device with a high degree of freedom in the size of pixel electrodes. A liquid crystal display device (1) of the present invention includes a first substrate (11) having a plurality of pixel electrodes (2) affixed thereto, a second substrate (12) which is provided with an opposite electrode (3) that faces the pixel electrodes (2) and which faces the first substrate (11), and a liquid crystal layer (4) that is interposed between the first substrate (11) and the second substrate (12) and that contains vertical orientation type crystal molecules (14). The liquid crystal molecules (14) are aligned and tilted radially or concentrically with respect to each of the pixel electrodes (2) in response to the voltage applied between the pixel electrodes (2) and the opposite electrode (3).
    Type: Application
    Filed: March 31, 2010
    Publication date: April 19, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Shigeki Tanaka
  • Patent number: 8148200
    Abstract: A wire short-circuit defect during molding is prevented. A semiconductor device has a tab, a plurality of leads arranged around the tab, a semiconductor chip mounted over the tab, a plurality of wires electrically connecting the electrode pads of the semiconductor chip with the leads, and a molded body in which the semiconductor chip is resin molded. By further stepwise shortening the chip-side tip end portions of the leads as the first edge or side of the principal surface of the semiconductor chip goes away from the middle portion toward the both end portions thereof, and shortening the tip end portions of those of first leads corresponding to the middle portion of the first edge or side of the principal surface which are adjacent to second leads located closer to the both end portions of the first edge or side, the distances between second wires connected to the second leads and the tip end portions of the first leads adjacent to the second leads can be increased.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeki Tanaka, Kazuto Ogasawara
  • Publication number: 20120064441
    Abstract: A method for photo-alignment treatment in which at least the number of kinds of photo masks or the number of exposure that are necessary for domain division can be reduced. The method for forming domains 8A, 8B, which are sectioned with respect to alignment regulation directions 11A, 11B, on a surface of an alignment film material 1 that develops alignment regulation powers to align liquid crystal molecules in accordance with irradiation directions of light includes irradiating the alignment film material surface from different directions with different kinds of linear polarized light 9A, 9B that have different planes of vibration through different kinds of polarizing plates 4A, 4B, the polarizing plates having transmission axes 6A, 6B being flush with the planes of vibration, and being disposed corresponding to the domains, wherein a mask 3 comprises the polarizing plates, and a light shielding supporting frame 5 arranged to support the polarizing plates.
    Type: Application
    Filed: March 31, 2010
    Publication date: March 15, 2012
    Inventor: Shigeki Tanaka
  • Publication number: 20120019762
    Abstract: A liquid crystal display panel (50a) includes a pair of substrates arranged, facing each other, a liquid crystal layer provided between the pair of substrates, and a frame-like sealing member (25) configured to bond the pair of substrates with each other and enclose the liquid crystal layer. A cavity forming wall (18ba) is provided on one of the pair of substrates between the liquid crystal layer and the sealing member (25) and is configured to form a cavity region (C) therein by an upper end of the cavity forming wall contacting the other of the pair of substrates. The cavity region (C) is configured so that, when an excessive amount of a liquid crystal material which foims the liquid crystal layer is enclosed, the cavity forming wall is destroyed to cause a portion of the liquid crystal material to flow into the cavity region (C).
    Type: Application
    Filed: July 18, 2008
    Publication date: January 26, 2012
    Inventor: Shigeki Tanaka
  • Publication number: 20120002183
    Abstract: A local exposure apparatus for performing exposure processing on a specific area of a photosensitive film formed on a substrate includes a substrate conveyor configured to define a substrate conveying path and to horizontally convey the substrate along the substrate conveying path, a chamber configured to define an exposure processing space, a light source including a plurality of light-emitting elements linearly arranged above the substrate conveying path, a light emission drive unit configured to selectively drive one or more of the light-emitting elements of the light source, a substrate detector configured to detect the substrate conveyed by the substrate conveyor, and a control unit configured to control the light emission drive unit such that, when the specific area of the photosensitive film moves below the light source, only the light-emitting elements capable of irradiating the given area are driven to emit the light.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 5, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yoshiharu OTA, Shigeru MORIYAMA, Yuki MATSUMURA, Shigeki Tanaka
  • Publication number: 20110300670
    Abstract: The occurrence of a resin seal failure is suppressed. A molding step is carried out using a lead frame in which there are formed multiple air vent portions for discharging gas in each cavity formed in the upper die of a molding die to outside the cavity. The air vent portions are formed at positions overlapping with the other corner portions, arranged inside a gate portion of the cavity. Each of the air vent portions is led out from the other corner portions of the cavity to outside a clamp area and is extended along sides of the cavity, respectively, in the clamp area.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 8, 2011
    Inventors: Shigeki TANAKA, Atsushi Fujisawa, Masahiro Tani, Satoru Suzuki
  • Publication number: 20110226142
    Abstract: In a screen printer, printing frame for the screen printer and a preparation method therefor, the screen printer comprises a screen mesh, which is provided on a predetermined frame body so as to be stretched at a predetermined tensile strength, and a plate-making screen master, which is arranged on one of faces of the screen mesh, wherein the tensile strength at time of stretching the screen mesh is higher than that at time of arranging the screen master in the screen mesh.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 22, 2011
    Applicant: RISO KAGAKU CORPORATION
    Inventors: Hidetoshi MIMURA, Shigeki TANAKA, Yasuyuki MIKATSURA
  • Publication number: 20110223719
    Abstract: A wire short-circuit defect during molding is prevented. A semiconductor device has a tab, a plurality of leads arranged around the tab, a semiconductor chip mounted over the tab, a plurality of wires electrically connecting the electrode pads of the semiconductor chip with the leads, and a molded body in which the semiconductor chip is resin molded. By further stepwise shortening the chip-side tip end portions of the leads as the first edge or side of the principal surface of the semiconductor chip goes away from the middle portion toward the both end portions thereof, and shortening the tip end portions of those of first leads corresponding to the middle portion of the first edge or side of the principal surface which are adjacent to second leads located closer to the both end portions of the first edge or side, the distances between second wires connected to the second leads and the tip end portions of the first leads adjacent to the second leads can be increased.
    Type: Application
    Filed: May 25, 2011
    Publication date: September 15, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shigeki Tanaka, Kazuto Ogasawara