Abstract: An asynchronous transfer mode (ATM) cell synchronizing method and circuit used in a digital network system in which: an 8 bit ATM cell stream of a received signal is inputted into a five-stage D flip-flop and outputted to a first adder (exclusive OR) circuit through a remainder operation circuit; the adder circuit evaluates exclusive OR of the output of the remainder operation circuit and the inputted 8 bit ATM cell stream, the result of such an evaluation is inputted into a one-stage D flip-flop through a second adder; and the output of this one-stage D flip-flop is inputted into a CRC arithmetic operation circuit having a generating polyominal X.sup.8 +X.sup.2 +) X+1 and also into a decoder. The output of the CRC arithmetic operation circuit is inputted back to the second adder, and a cell synchronizing pulse is outputted from the decoder.

Abstract: A method and device for detecting a cyclic code which detects an n-bit cyclic code or shortened cyclic code based on a degree-m generating polynomial or code with a predetermined bit pattern added to the cyclic code or shortened cyclic code in the bit sequence of a signal containing those codes by utilizing the principle that the remainder of division of those codes by the generating polynomial is zero or the added bit pattern.The method divides serially input receive data by the generating polynomial successively, and removes the remainder of division of X.sup.n by the generating polynomial from the remainder of the division of the bits up to the current bit if the nth bit before the current bit is 1 for each of the nth bit from the first bit and subsequent bits of the receive data.