Abstract: At least one capacitor cell for absorbing noise on a power supply voltage and a ground potential are arranged between at least one logic cell which configures a semiconductor integrated circuit and a power supply main line for supplying a power supply voltage to the logic cell. The power supply voltage where noises are suppressed by the capacitor cells is supplied to the logic cell, thus improving performance of the semiconductor integrated circuit. In addition, a distribution density of the capacitor cell or a capacity of the capacitor cell increases as the capacitor cell is separated from the power supply main line. A predetermined power supply voltage is supply to the logic cell which is separated from the power supply main line, so that a decrease in operation speed of the semiconductor integrated circuit can be suppressed.

Abstract: An operation timing verifying apparatus and program for accurately verifying operation timings of a semiconductor integrated circuit in design with suppressing design time and cost. The operation timing verifying apparatus and program sets an unreal corner condition that all delay elements present a maximum delay as an operating condition, performs operation timing analysis in the operating condition, thereby extracting an operation-violating circuit path, if any, from a circuit layout, sets a real corner condition that at least one element type of delay elements from among the delay elements present a maximum delay as the operating condition and performs the operation timing analysis on only the operation-violating circuit path to determine again whether an operation violation exists therein.

Abstract: An operation timing verifying apparatus and program for accurately verifying operation timings of a semiconductor integrated circuit in design with suppressing design time and cost. The operation timing verifying apparatus and program sets an unreal corner condition that all delay elements present a maximum delay as an operating condition, performs operation timing analysis in the operating condition, thereby extracting an operation-violating circuit path, if any, from a circuit layout, sets a real corner condition that at least one element type of delay elements from among the delay elements present a maximum delay as the operating condition and performs the operation timing analysis on only the operation-violating circuit path to determine again whether an operation violation exists therein.

Abstract: At least one capacitor cell for absorbing noise on a power supply voltage and a ground potential are arranged between at least one logic cell which configures a semiconductor integrated circuit and a power supply main line for supplying a power supply voltage to the logic cell. The power supply voltage where noises are suppressed by the capacitor cells is supplied to the logic cell, thus improving performance of the semiconductor integrated circuit. In addition, a distribution density of the capacitor cell or a capacity of the capacitor cell increases as the capacitor cell is separated from the power supply main line. A predetermined power supply voltage is supply to the logic cell which is separated from the power supply main line, so that a decrease in operation speed of the semiconductor integrated circuit can be suppressed.