Patents by Inventor Shigeko Hashimoto

Shigeko Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiprocessor synchronization and coherency control system
    Patent number: 6466988
    Abstract: A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Naonobu Sukegawa, Kouki Uwano, Shigeko Hashimoto, Masakazu Fukagawa, Eiki Kamada
  • Parallel processor synchronization and coherency control method and system
    Patent number: 6263406
    Abstract: Each of processors in a multiprocessor system has a circuit for sending a synchronizing signal to a storage controller (SC) connected thereto when executing a synchronization instruction such as a start, end or barrier synchronization instruction. Each of the SCs has a circuit for notifying the corresponding processor of establishment of a synchronization upon detection of completion of a check to be made by an address management table FAA and of the issuing of necessary cache cancel requests corresponding to a store instruction issued before the synchronization instruction and upon recognition of the fact that all the processors have sent their synchronizing signals and that the issuing of all the cache cancel requests have been complete.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: July 17, 2001
    Assignee: Hitachi, LTD
    Inventors: Kohki Uwano, Shigeko Hashimoto, Naonobu Sukegawa, Tadaaki Isobe, Miki Miyaki, Tatsuya Ichiki
  • Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors
    Patent number: 5857110
    Abstract: In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: January 5, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Tadayuki Sakakibara, Teruo Tanaka, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Hashimoto, Yasuhiro Inagami, Yoshiko Tamaki
  • Interprocessor priority control system for multivector processor
    Patent number: 5617575
    Abstract: In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: April 1, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Tadayuki Sakakibara, Teruo Tanaka, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Hashimoto, Yasuhiro Inagami, Yoshiko Tamaki