Patents by Inventor Shigemi Chimura
Shigemi Chimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6842859Abstract: Upon receiving an encipherment command, an enciphered authentication data generation circuit generates an enciphered authentication data based on a basic authentication data including a random number portion using an encipherment rule. The encipherment rule changes according to the number of supplied encipherment commands. A transmission circuit 7 transmits the enciphered authentication data. A reception circuit 9 receives the enciphered authentication data transmitted from a second device 300. A prohibition command output circuit 11 determines whether the enciphered authentication data transmitted from the second device 300 matches with an enciphered authentication data that would be generated if the same number of encipherment commands were supplied to an enciphered authentication data generation circuit of a first device 200, and outputs a prohibition command to prohibit a transmission of the data to be transmitted when the determination result is negative.Type: GrantFiled: January 30, 1998Date of Patent: January 11, 2005Assignee: Rohm Co., Ltd.Inventors: Junichi Hikita, Yoshihiro Ikefuji, Shigemi Chimura
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Patent number: 6679424Abstract: A memory (1) in a non contact type IC card (100) includes a data protection region (B2) storing data requiring security and an region (B1) storing other data. A main control circuit (2) generates data to be stored and designates a location for data storage in the region (B1) or the data protection region (B2) according to a content of the data. An address non selecting circuit (4) selects whether the generated data is to be written into the location in the data protection region (B2) designated by the main control circuit (2) according to a state of a state setting circuit (3).Type: GrantFiled: November 5, 2002Date of Patent: January 20, 2004Assignee: Rohm Co., Ltd.Inventors: Junichi Hikita, Yoshihiro Ikefuji, Shigemi Chimura, Haruo Taguchi
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Patent number: 6624743Abstract: In a non-contact IC card, a driving portion 5 sequentially switches a resonance frequency of a resonance circuit 1. A reference voltage generating portion 6 receives an output voltage of resonance circuit 1 for outputting a prescribed reference voltage. An output value measuring portion 7 measures a magnitude of the output voltage of resonance circuit 1 at each resonance frequency using the reference voltage as a reference. An output value storing portion 8 stores a measurement value (an output value). A manner determining portion 9 selects the largest one of the output values stored in output value storing portion 8, and determines a switching manner corresponding thereto as a suitable switching manner. Thus, the suitable switching manner allowing the most efficient power supply can be achieved.Type: GrantFiled: June 9, 1999Date of Patent: September 23, 2003Assignee: Rohm Co., LTDInventors: Yoshihiro Ikefuji, Shigemi Chimura, Satoshi Yoshioka
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Publication number: 20030066895Abstract: A memory (1) in a non contact type IC card (100) includes a data protection region (B2) storing data requiring security and an region (B1) storing other data. A main control circuit (2) generates data to be stored and designates a location for data storage in the region (B1) or the data protection region (B2) according to a content of the data. An address non selecting circuit (4) selects whether the generated data is to be written into the location in the data protection region (B2) designated by the main control circuit (2) according to a state of a state setting circuit (3).Type: ApplicationFiled: November 5, 2002Publication date: April 10, 2003Applicant: ROHM CO., LTD.Inventors: Junichi Hikita, Yoshihiro Ikefuji, Shigemi Chimura, Haruo Taguchi
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Patent number: 6498923Abstract: A data communication apparatus according to the present invention can be used both in one-wave mode and two-wave mode, and includes: first and second tuning circuits (1, 2); a power supply circuit (3) connected to first tuning circuit (1) for generating power by a signal received by first tuning circuit (1); an information processing circuit (15) connected to first tuning circuit (1) or second tuning circuit (2) through a switching circuit (6) and including a detection circuit (7), a decoder (8), an encoder (10) and the like. Information processing circuit (15) includes a switch control circuit (14) detecting if the mode of the received radio wave is one-wave mode or two-wave mode in accordance with an output from first tuning circuit (1) and controlling switching circuit (6) such that detection circuit (7) is connected to one of first and second tuning circuits (1, 2).Type: GrantFiled: August 24, 1999Date of Patent: December 24, 2002Assignee: Rohm Co., Ltd.Inventors: Yoshihiro Ikefuji, Shigemi Chimura, Haruo Taguchi
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Patent number: 6478228Abstract: A highly rigid ceramic frame (38) is embedded in a layer of a core member (34). An IC chip (42) is held inside (38a) via an elastic member (40). IC chip 42 arranged inside (38a) will not be greatly deformed even when a strong bending, torsional, or pressing force is applied to the IC card (30). An impact, when exerted on the IC card (30), will not be directly conveyed to the IC chip (42). A coil (44) formed by printing and the like is provided at an upper end face (38b) of the ceramic frame (38). The coil (44) is connected to the IC chip (42) by a wire (46). By forming the IC chip (42), the ceramic frame (38) and the coil (44) integrally in advance, the workability in fabrication is improved. Therefore, a circuit chip mounted card of high reliability and low fabrication cost can be provided.Type: GrantFiled: June 24, 1999Date of Patent: November 12, 2002Assignee: Rohm Co., LTDInventors: Yoshihiro Ikefuji, Shigemi Chimura, Toyokazu Komuro
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Publication number: 20020162893Abstract: A memory (1) in a non contact type IC card (100) includes a data protection region (B2) storing data requiring security and an region (B1) storing other data. A main control circuit (2) generates data to be stored and designates a location for data storage in the region (B1) or the data protection region (B2) according to a content of the data. An address non selecting circuit (4) selects whether the generated data is to be written into the location in the data protection region (B2) designated by the main control circuit (2) according to a state of a state setting circuit (3).Type: ApplicationFiled: July 20, 1999Publication date: November 7, 2002Inventors: JUNICHI HIKITA, YOSHIHIRO IKEFUJI, SHIGEMI CHIMURA, HARUO TAGUCHI
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Patent number: 6464145Abstract: An IC card produces electric power by rectifying a high-frequency signal received from a reader/writer. A MOS transistor is connected to an antenna and the received signal is rectified by the parasitic diode of the MOS transistor. The capacitance accompanying the transistor is added to the capacitance of an input tuning capacitor. Switching the on/off state of the transistor causes the capacitance added to that of the tuning capacitor to change; accordingly, the input tuning frequency changes and the relation between the input tuning frequency and the frequency of the received high-frequency signal changes. As a result, the amplitude of the received high-frequency signal changes and thus the obtained power also changes.Type: GrantFiled: May 4, 2000Date of Patent: October 15, 2002Assignee: Rohm Co., Ltd.Inventor: Shigemi Chimura
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Publication number: 20020137463Abstract: A data communication apparatus according to the present invention can be used both in one-wave mode and two-wave mode, and includes: first and second tuning circuits (1, 2); a power supply circuit (3) connected to first tuning circuit (1) for generating power by a signal received by first tuning circuit (1); an information processing circuit (15) connected to first tuning circuit (1) or second tuning circuit (2) through a switching circuit (6) and including a detection circuit (7), a decoder (8), an encoder (10) and the like. Information processing circuit (15) includes a switch control circuit (14) detecting if the mode of the received radio wave is one-wave mode or two-wave mode in accordance with an output from first tuning circuit (1) and controlling switching circuit (6) such that detection circuit (7) is connected to one of first and second tuning circuits (1, 2).Type: ApplicationFiled: August 24, 1999Publication date: September 26, 2002Inventors: YOSHIHIRO IKEFUJI, SHIGEMI CHIMURA, HARUO TAGUCHI
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Patent number: 6422473Abstract: Oppositely arranged bumps (82,84) are electrically connected by connecting two IC chips (76,78) through an anisotropic conductor (80) to form an IC chip module (74). With IC chip module (74) having such structure, two IC chips (76,78) provided with functions of a processing portion and an antenna are simply stacked to provide a function for communication, and arrangement of interconnection outside IC chip (76,78) is not necessary. Thus, accidental breakage of the interconnection is avoided and assembly is extremely facilitated. Therefore, a circuit chip mounted card with higher reliability and reduced manufacturing cost and the like can be provided.Type: GrantFiled: June 22, 1999Date of Patent: July 23, 2002Assignee: Rohm Co., Ltd.Inventors: Yoshihiro Ikefuji, Shigemi Chimura, Hiroharu Okada
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Publication number: 20020070280Abstract: Oppositely arranged bumps (82,84) are electrically connected by connecting two IC chips (76,78) through an anisotropic conductor (80) to form an IC chip module (74). With IC chip module (74) having such structure, two IC chips (76,78) provided with functions of a processing portion and an antenna are simply stacked to provide a function for communication, and arrangement of interconnection outside IC chip (76,78) is not necessary. Thus, accidental breakage of the interconnection is avoided and assembly is extremely facilitated. Therefore, a circuit chip mounted card with higher reliability and reduced manufacturing cost and the like can be provided.Type: ApplicationFiled: June 22, 1999Publication date: June 13, 2002Inventors: YOSHIHIRO IKEFUJI, SHIGEMI CHIMURA, HIROHARU OKADA
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Publication number: 20010045468Abstract: An IC card which can normally perform the next data communication processing if there is an abnormality in data communication is provided. When abnormality determination circuit 1 determines that the previous data reception state is normal, before newly received data to be held DA is stored in a data holding memory 2, IC card 100 saves data in a region to write data DA into a data protection memory 3. Meanwhile if abnormality determination circuit 1 determines that the previous data reception state is abnormal, data in data holding memory 2 is recovered using data which has been saved in data protection memory 3 before accessing to data holding memory 2 is started.Type: ApplicationFiled: June 17, 1999Publication date: November 29, 2001Inventors: YOSHIHIRO IKEFUJI, SHIGEMI CHIMURA, HARUO TAGUCHI
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Patent number: 6181001Abstract: A circuit chip mounted card has a processing-circuit layer 106 in which is constructed a processing unit including a non-volatile memory, a modulation/demodulation circuit and a capacitor for providing a process associated with communication. In the processing-circuit layer is also constructed a coil 44 of a looped metal wire. Communicating function is completely provided only by a single IC chip 104 with the function of the processing unit and that of an antenna integrated therewith. Thus IC chip 104 does not require external wiring and will thus not suffer from an accidentally cut-off wire or the like. It is also dispensed with an operation to connect wires so that the card can extremely readily be fabricated. Thus a circuit chip mounted card can be obtained which is highly reliable and reduces the cost for manufacturing the same.Type: GrantFiled: June 24, 1999Date of Patent: January 30, 2001Assignee: Rohm Co., Ltd.Inventors: Yoshihiro Ikefuji, Shigemi Chimura, Hiroharu Okada
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Patent number: 5396639Abstract: A one-chip microcomputer according to the present invention is provided with an initial reset circuit for producing a first initial reset signal having a first reset period and a second initial reset signal having a second reset period which is longer than the first reset period, an access circuit for gaining access to an address in a nonvolatile memory such as a built-in ROM to read data therefrom, and I/O buffer circuits. A storage circuit and an I/O buffer connected to a programmable I/O terminal are provided in the I/O buffer circuit and a function of the I/O terminal with options is selected in conformity with the data set in the storage circuit. The data stored at a predetermined address in the nonvolatile memory is transferred to the storage circuit by operating the access circuit until the termination of the reset period of the second initial reset signal after the termination of the first reset period of the first initial reset signal.Type: GrantFiled: September 16, 1991Date of Patent: March 7, 1995Assignee: Rohm Co., Ltd.Inventors: Yoshiaki Suenaga, Shigemi Chimura, Hiroaki Masumoto
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Patent number: 5208492Abstract: The improved CMOS output circuit has an enhancement-type PMOS and an enhancement-type NMOS connected in order between a power supply line and a reference potential line and that has the junction between the PMOS and the NMOS connected to an output terminal. The PMOS is such that a P-type region is provided in the back gate region to form a diode, with the back gate region being connected to the power supply line via the diode. A switch circuit is inserted between the gate of this PMOS and said junction or the output terminal. When a voltage higher than the voltage on the power supply line is applied to the output terminal, the applied voltage will turn on the switch circuit.Type: GrantFiled: February 5, 1992Date of Patent: May 4, 1993Assignee: Rohm Co., Ltd.Inventors: Hiroaki Masumoto, Shigemi Chimura