Patents by Inventor Shigemitsu Maruno

Shigemitsu Maruno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6635938
    Abstract: A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride film, a sidewall insulating film is formed. By epitaxial growth, selective silicon films of a prescribed film thickness are formed on source and drain regions. During this period, silicon islands are not deposited on the surface of sidewall insulating film. Consequently, a semiconductor device including a transistor of a superior electrical insulation can be obtained.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: October 21, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takumi Nakahata, Shigemitsu Maruno, Taisuke Furukawa, Naruhisa Miura, Toshiyuki Oishi, Yasunori Tokuda
  • Patent number: 6373108
    Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: April 16, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Satoshi Yamakawa, Yasunori Tokuda, Takumi Nakahata, Taisuke Furukawa, Shigemitsu Maruno
  • Publication number: 20020000622
    Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.
    Type: Application
    Filed: March 1, 1999
    Publication date: January 3, 2002
    Inventors: SATOSHI YAMAKAWA, YASUNORI TOKUDA, TAKUMI NAKAHATA, TAISUKE FURUKAWA, SHIGEMITSU MARUNO
  • Patent number: 6232192
    Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: May 15, 2001
    Assignee: Mitubishi Denki Kabushiki Kaisha
    Inventors: Satoshi Yamakawa, Yasunori Tokuda, Takumi Nakahata, Taisuke Furukawa, Shigemitsu Maruno
  • Patent number: 6228728
    Abstract: According to the inventive method of fabricating a semiconductor device, a silicon substrate is exposed to an oxygen atmosphere of 600° C. to 900° C., for forming silicon oxide films on surfaces of epitaxial silicon layers and those of silicon fragments. Thus, a method of fabricating a semiconductor device capable of preventing electrodes thereof from shorting can be provided.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: May 8, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Taisuke Furukawa, Takumi Nakahata, Shigemitsu Maruno, Kohei Sugihara, Yasutaka Nishioka, Satoshi Yamakawa, Yasunori Tokuda