Patents by Inventor Shigenari Aoki

Shigenari Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8298920
    Abstract: A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: October 30, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Shigenari Aoki
  • Publication number: 20110189798
    Abstract: A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer.
    Type: Application
    Filed: April 15, 2011
    Publication date: August 4, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Shigenari Aoki
  • Patent number: 7947563
    Abstract: A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: May 24, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Shigenari Aoki
  • Publication number: 20070202664
    Abstract: The present invention provides a chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, marks different every chip are formed in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer.
    Type: Application
    Filed: February 9, 2007
    Publication date: August 30, 2007
    Inventor: Shigenari Aoki
  • Patent number: 6579734
    Abstract: A semiconductor device is provided which is obtained by wire bonding without any drop in wire bonding characteristics. A bonding pad is prepared on which a wire bonding region and a test region that is separate from the wire bonding region are defined. A characteristic test is performed on the semiconductor element in the test region. Wire bonding in which a wire is connected is performed in the wire bonding region.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: June 17, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shigenari Aoki
  • Publication number: 20020146898
    Abstract: A semiconductor device is provided which is obtained by wire bonding without any drop in wire bonding characteristics. A bonding pad is prepared on which a wire bonding region and a test region that is separate from the wire bonding region are defined. A characteristic test is performed on the semiconductor element in the test region. Wire bonding in which a wire is connected is performed in the wire bonding region.
    Type: Application
    Filed: July 24, 2001
    Publication date: October 10, 2002
    Inventor: Shigenari Aoki