Abstract: A structure and method for fabricating an integrate circuit crown structure for use in a DRAM cell on a substrate comprising a common source/drain region (18) disposed within a substrate (12), the common source/drain region (18) connected to a bitline (22), a gate oxide (28) disposed over the common source/drain region (18) and forming at least two wordline gates (30), at least two storage node source/drains (20) adjacent to said gates (30) and contacted by storage node contacts (38) and a storage node bowl (36), the bowl being formed within adjacent supporting layers formed over said wordline gates wherein the storage node bowl (36) is formed, and electrically isolated from, the bitline (22) without being exposed to etching agents during its formation and without forming a wine glass stem structure and a crown extending from the top of the storage node bowl (36), is disclosed.

Abstract: A structure and method for fabricating an integrated circuit crown structure for use in a DRAM cell on a substrate comprising a common source/drain region (18) disposed within a substrate (12), the common source/drain region (18) connected to a bitline (22), a gate oxide (28) disposed over the common source/drain region (18) and forming at least two wordline gates (30), at least two storage node source/drains (20) adjacent to said gates (30) and contacted by storage node contacts (38) and a storage node bowl (36), the bowl being formed within adjacent supporting layers formed over said wordline gates wherein the storage node bowl (36) is formed, and electrically isolated from, the bitline (22) without being exposed to etching agents during its formation and without forming a wine glass stem structure and a crown extending from the top of the storage node bowl (36), is disclosed.

Abstract: A method for fabricating a memory cell includes forming a first access line (16) for a storage node (140, 210) and forming a second access line (82) operable to access the storage node (140, 210) in connection with the first access line (16). The first access line (16) includes a first terminal (32) and a second terminal (34). The second access line (82) includes a conductive layer (70) connected to the first terminal (32) of the first access line (16). An opening (88) is formed in the second access line (82) for connection of the storage node (140, 210) to the second terminal (34) of the first access line (16). A sidewall (92) is formed in the opening (88) to form a contact hole (94) insulated from the conductor (70) of the second access line (82). The storage node (140, 210) is formed having a self-aligned contact (102) formed in the contact hole (94) and connected to the second terminal (34) of the first access line (16).