Patents by Inventor Shigenobu Taira

Shigenobu Taira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6356475
    Abstract: A method of reading data from a ferroelectric memory has a memory cell which uses a ferroelectric capacitor as a storage medium. The method includes the steps of (a) applying first and second electric fields having opposite directions to the ferroelectric capacitor, wherein polarization of the ferroelectric capacitor is changed according to a variation of the first and second electric fields; and (b) reading out the data stored in the memory cell by detecting a variation of the polarization of the ferroelectric capacitor.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: March 12, 2002
    Assignee: Fujitsu Limited
    Inventors: Tetsuro Tamura, Kazuaki Takai, Shigenobu Taira
  • Patent number: 6144579
    Abstract: A ferroelectric memory device includes a channel region formed in a substrate having a first conductivity type, a first diffusion region formed in the substrate at a first side of the channel region with a second, opposite conductivity type, a second diffusion region formed in the substrate at a second side of said channel region with the second conductivity type, a ferroelectric film formed on the substrate so as to cover the channel region, and a gate electrode provided on the ferroelectric film, wherein the channel region has the second conductivity type.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: November 7, 2000
    Assignee: Fujitsu Limited
    Inventor: Shigenobu Taira
  • Patent number: 6049477
    Abstract: A ferroelectric memory device includes a channel region formed in a substrate having a first conductivity type, a first diffusion region formed in the substrate at a first side of the channel region with a second, opposite conductivity type, a second diffusion region formed in the substrate at a second side of said channel region with the second conductivity type, a ferroelectric film formed on the substrate so as to cover the channel region, and a gate electrode provided on the ferroelectric film, wherein the channel region has the second conductivity type.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: April 11, 2000
    Assignee: Fujitsu Limited
    Inventor: Shigenobu Taira
  • Patent number: 5737261
    Abstract: A ferroelectric memory using residual polarization of a ferroelectric film. The memory includes a semiconductor substrate of one conductive type; a write transistor having a source region and a drain region of another conductive type formed at a surface of the semiconductor substrate; a read transistor having a source region and a drain region of another conductive type formed at the surface of the semiconductor substrate; and a storage transistor having a source region and a drain region of one conductive type at the surface of the semiconductor substrate. One source or drain region of the write transistor is connected to a gate electrode of the storage transistor, and one source or drain region of the storage transistor is connected to one source or drain region of the read transistor so as to provide a memory cell.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: April 7, 1998
    Assignee: Fujitsu Limited
    Inventor: Shigenobu Taira
  • Patent number: 4449158
    Abstract: An input protection circuit which protects the gate of a MIS transistor from breakdown due to an excessively high voltage being applied thereto. The input protection circuit includes a first resistor and a second resistor connected in series between a input terminal and a gate of the MIS transistor, a first protection transistor provided between a first connecting point between the first and second resistors and one side of the power supply, and a second protection transistor provided between a second connecting point between the second resistor and the gate of the MIS transistor the other side of the power supply. The first protection transistor has a large mutual conductance gm, while the second protection transistor has a low breakdown voltage.
    Type: Grant
    Filed: December 4, 1981
    Date of Patent: May 15, 1984
    Assignee: Fujitsu Limited
    Inventor: Shigenobu Taira
  • Patent number: 4446384
    Abstract: A MIS device including a substrate bias generating circuit comprising: an oscillating circuit for generating clock signals; a pumping circuit comprised of a charging and discharging circuit and a bias circuit, for absorbing charges in a semiconductor substrate, and; a clamp circuit for clamping the potential of the substrate at a desired level.
    Type: Grant
    Filed: January 10, 1983
    Date of Patent: May 1, 1984
    Assignee: Fujitsu Limited
    Inventor: Shigenobu Taira
  • Patent number: 4378506
    Abstract: A MIS device including a substrate bias generating circuit comprising: an oscillating circuit for generating clock signals; a pumping circuit comprised of a charging and discharging circuit and a bias circuit, for absorbing charges in a semiconductor substrate, and; a clamp circuit for clamping the potential of the substrate at a desired level.
    Type: Grant
    Filed: August 22, 1980
    Date of Patent: March 29, 1983
    Assignee: Fujitsu Limited
    Inventor: Shigenobu Taira
  • Patent number: 4014652
    Abstract: An automatic analytic apparatus of liquids has a liquid analyzer; a gas-admissible tube connected to the analyzer so as to conduct a liquid thereto; and means to collect a specified amount of liquid sample being analyzed, and, each time the collected amount of said liquid reaches said specified amount, automatically carry the liquid sample batch forward with a prescribed amount of air or any other inert gas interposed between the adjacent batches of said liquid sample, thus continuously passing alternate series of flowing liquid and gas batches respectively having a predetermined quantity through the above-mentioned tube.
    Type: Grant
    Filed: September 18, 1975
    Date of Patent: March 29, 1977
    Assignee: Showa Denko Kabushiki Kaisha
    Inventors: Wataru Ishibashi, Shigenobu Taira, Ken Migita