Abstract: A data managing device with a single chip that includes: first hardware that authenticates security of communication performed by a data processing apparatus that houses the data managing device; second hardware that performs different processing from processing performed by the first hardware; and third hardware that receives an update program for a program executed by any one of the first hardware and the second hardware, from a data providing apparatus with which security of communication is authenticated by the first hardware, and updates the program by the update program.

Abstract: A data managing device with a single chip that includes: first hardware that authenticates security of communication performed by a data processing apparatus that houses the data managing device; second hardware that performs different processing from processing performed by the first hardware; and third hardware that receives an update program for a program executed by any one of the first hardware and the second hardware, from a data providing apparatus with which security of communication is authenticated by the first hardware, and updates the program by the update program.

Abstract: A phase difference-detecting apparatus for detecting a relative distance between a pair of focused images obtained from subject luminous flux passed through an objective lens to thereby judge a focusing state of the objective lens. The apparatus includes a pair of signal generating sections which receive the subject flux and provide first and second time series signals. A switching-capacitor integrator is provided including a plurality of capacitive elements and switching elements for intermittently connecting the capacitive elements to each other, and for receiving the first and second time series signals. A control device compares the sizes of the first and second time series signals with each other to thereby generate a control signal corresponding to a relation of size between the first and second time series signals.

Abstract: The packing density of a logic LSI based on standard cell methodology is increased by partially overlapping two adjoining cells so as to have common terminal regions to be connected to the wirings for supplying power. To this end, the pattern of the terminal region at a side edge of the cells in the row direction is standardized in its shape, size and position in each cell. The cells are registered in the cell library of a CAD system, together with a newly introduced additional symbol to indicate the region which may be overlapped during chip design operation using a display.

Abstract: A large scale semiconductor integrated circuit and its wiring method employing a grid system where the layout space is partitioned in the form of a grid by vertical and horizontal line group having an interval larger than a length corresponding to a minimum dimension for a patterning in a manufacturing process; wiring patterns for making connection between each cell which is a unit of layout are depicted on such vertical and horizontal lines; and wirings are made on the basis of the wiring patterns. An interval (d) of these vertical and horizontal lines of the grid is the greatest common factor of the minimum wiring pitches of several overlapped wiring layers and is selected to a dimension which is smaller than said wiring pitch; and the vertical and horizontal line patterns are depicted on the vertical and horizontal lines having the same interval.

Abstract: A complementary metal-oxide semiconductor comprises at least one P channel MOSFET and at least one N channel MOSFET. In the semiconductor at least one additional doped portion is formed close to at least one of the P and N channel MOSFETs at a small part of the region which is driven by the voltage supply. The additional doped portion is directly connected to the voltage supply.