Abstract: A computer system of a multi-operation-system (multi-OS) has a main memory having a memory area for a first OS and a memory area for a second OS, both the areas being independent from each other, and a plurality of I/O devices divisionally allocated to the first OS and the second OS. The first OS is loaded in the first OS memory area, and thereafter when the first OS is operated, the second OS is loaded in the second OS memory area and initialized. When the first OS is operated, the first OS hardware resources and the second OS hardware resources are registered by the first OS. Thereafter when the first OS is operated, the first OS inhibits the registration of an interrupt number already allocated to the second OS I/O device. In response to an interrupt request from a second OS I/O device, the second OS starts operating.

Abstract: An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.

Abstract: A computer system of a multi-operation-system (multi-OS) has a main memory having a memory area for a first OS and a memory area for a second OS, both the areas being independent from each other, and a plurality of I/O devices divisionally allocated to the first OS and the second OS. The first OS is loaded in the first OS memory area, and thereafter when the first OS is operated, the second OS is loaded in the second OS memory area and initialized. When the first OS is operated, the first OS hardware resources and the second OS hardware resources are registered by the first OS. Thereafter when the first OS is operated, the first OS inhibits the registration of an interrupt number already allocated to the second OS I/O device. In response to an interrupt request from a second OS I/O device, the second OS starts operating.

Abstract: An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.

Abstract: A computer system of a multi-operation-system (multi-OS) has a main memory having a memory area for a first OS and a memory area for a second OS, both the areas being independent from each other, and a plurality of I/O devices divisionally allocated to the first OS and the second OS. The first OS is loaded in the first OS memory area, and thereafter when the first OS is operated, the second OS is loaded in the second OS memory area and initialized. When the first OS is operated, the first OS hardware resources and the second OS hardware resources are registered by the first OS. Thereafter when the first OS is operated, the first OS inhibits the registration of an interrupt number already allocated to the second OS I/O device. In response to an interrupt request from a second OS I/O device, the second OS starts operating.

Abstract: An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.

Abstract: A computer system of a multi-operation-system (multi-OS) has a main memory having a memory area for a first OS and a memory area for a second OS, both the areas being independent from each other, and a plurality of I/O devices divisionally allocated to the first OS and the second OS. The first OS is loaded in the first OS memory area, and thereafter when the first OS is operated, the second OS is loaded in the second OS memory area and initialized. When the first OS is operated, the first OS hardware resources and the second OS hardware resources are registered by the first OS. Thereafter when the first OS is operated, the first OS inhibits the registration of an interrupt number already allocated to the second OS I/O device. In response to an interrupt request from a second OS I/O device, the second OS starts operating.

Abstract: An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.

Abstract: A computer system of a multi-operation-system (multi-OS) has a main memory having a memory area for a first OS and a memory area for a second OS, both the areas being independent from each other, and a plurality of I/O devices divisionally allocated to the first OS and the second OS. The first OS is loaded in the first OS memory area, and thereafter when the first OS is operated, the second OS is loaded in the second OS memory area and initialized. When the first OS is operated, the first OS hardware resources and the second OS hardware resources are registered by the first OS. Thereafter when the first OS is operated, the first OS inhibits the registration of an interrupt number already allocated to the second OS I/O device. In response to an interrupt request from a second OS I/O device, the second OS starts operating.

Abstract: A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails.

Abstract: A computer and a backup computer exchange periodic report signal transmissions by way of SVP115. When there is no periodic report signal transmission from the main computer, the backup computer makes a main computer status inquiry and if one location is malfunctioning resets the main computer by way of the SVP115 and continues the processing. When permanent damage is present, the SVP115 continually resets the main computer and controls MOS switches of the common disk unit to isolate the SCSI from the main computer and continue the main computer processing.

Abstract: A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B).

Abstract: A computer system and method for enabling memory expansion without shutting off the computer system are disclosed. The computer system has a dual memory configuration and supports memory insertion and extraction while being on-line. The memory content of one system may be copied to the memory of another system according to a predetermined priority or after a predetermined delay. Memory may be used efficiently during the insertion or extraction by securing a status management table expansion area in an expanded portion of memory. Memory may be expanded in computer systems that do not have an open memory slot by replacing the installed memory with a memory having a larger capacity.

Abstract: A main memory managing arrangement involves allotting a request program to one of three distinct areas of main memory by looking in an area managing table which stores head addresses and the capacities of the respective areas. The areas allocated in main memory correspond to a single OS area, a single first class program area and a single second class program area. An empty page managing table is also provided for indicating the presence or absence of an empty area conformable to a request in an allocated area. A request program is allocated to the allocated area when the presence of the empty area of required capacity is determined. The memory capacity for a resident program can be assured independently of the memory capacities for other programs to enhance reliability conformable to real-time process computers.