Patents by Inventor Shigenori Katayama

Shigenori Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6750476
    Abstract: A substrate device has, on a substrate, a first conductive film, a first insulating film formed thereon, a second insulating film bonded thereon, and a second conductive film formed thereon. A contact hole connecting the first and second conductive films is opened so as to penetrate through a bonding interface thereof. The area of the contact hole penetrating through the bonding interface is not eroded by an etching solution. Thus, where manufacturing a substrate device in which a contact hole penetrating through a bonding interface needs to be formed, it is unlikely that a defect will occur in the area where the contact hole passing through the bonding interface, thereby enhancing device reliability and manufacturing yield.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: June 15, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Shigenori Katayama
  • Patent number: 6750836
    Abstract: The invention provides a liquid crystal panel substrate having transistors and reflectors connected to the transistors on a substrate to allow bright reflection display of high quality at wide viewing angles by providing the most suitable reflection characteristics to the reflectors. Under the reflectors, first conductive layers are overlaid in regions corresponding to the reflectors and formed in a concave-convex condition by forming a large number of openings. Also, in a plan view, a light-shielding film covering gaps between the reflectors is formed of the second conductive layer, and may have no openings.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: June 15, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Shigenori Katayama, Ryo Ishii
  • Publication number: 20030180979
    Abstract: An electrooptical substrate device has pixel electrodes and pixel-switching TFTs connected thereto, on a substrate. The TFT is a P-channel TFT of an SOI structure that does not have a body contact. Due to this, a transistor is architected in each pixel that is suited to broaden the opening area in each pixel, and having comparatively high performance, thereby enabling bright, high-quality image display.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 25, 2003
    Applicant: Seiko Epson Corporation
    Inventor: Shigenori Katayama
  • Patent number: 6605827
    Abstract: An electrooptical substrate device has pixel electrodes and pixel-switching TFTs connected thereto, on a substrate. The TFT is a P-channel TFT of an SOI structure that does not have a body contact. Due to this, a transistor is architected in each pixel that is suited to broaden the opening area in each pixel, and having comparatively high performance, thereby enabling bright, high-quality image display.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: August 12, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Shigenori Katayama
  • Publication number: 20030137613
    Abstract: To provide an electrooptic device which can reliably suppress a substrate floating effect, such as a parasitic bipolar phenomenon, in an SOI-MIS transistor, and which has superior electrical characteristics. An electrooptic device (liquid crystal light valve) of the present invention uses, as one substrate, a composite substrate including a quartz substrate (main substrate 10A) having a first coefficient of thermal expansion, an insulating layer (insulating underlayer 12) formed on the quartz substrate, and a single-crystal silicon layer (semiconductor layer 1a) formed on the insulating layer and having a second coefficient of thermal expansion. A TFT 30 that uses the single-crystal silicon layer as a channel region 1a′ is formed on the insulating layer, and at least one line defect D exists in the single-crystal silicon layer that forms the channel region 1a′.
    Type: Application
    Filed: December 9, 2002
    Publication date: July 24, 2003
    Applicant: SEIKO EPSON CORPORATION.
    Inventor: Shigenori Katayama
  • Patent number: 6593626
    Abstract: A channel region of a semiconductor layer has an extending portion. The terminal of the extending portion is connected to a first contact hole. The first contact hole is connected to a connecting line. The connecting line is connected to the first contact hole at one end, as described above, extends directly above a capacitor line in the Y direction, and is connected to the capacitor line via a second contact hole at this position.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: July 15, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Shigenori Katayama, Masahiro Yasukawa
  • Publication number: 20020153569
    Abstract: An electrooptical substrate device has pixel electrodes and pixel-switching TFTs connected thereto, on a substrate. The TFT is a P-channel TFT of an SOI structure that does not have a body contact. Due to this, a transistor is architected in each pixel that is suited to broaden the opening area in each pixel, and having comparatively high performance, thereby enabling bright, high-quality image display.
    Type: Application
    Filed: March 20, 2002
    Publication date: October 24, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shigenori Katayama
  • Publication number: 20020145140
    Abstract: A substrate device has, on a substrate, a first conductive film, a first insulating film formed thereon, a second insulating film bonded thereon, and a second conductive film formed thereon. A contact hole connecting the first and second conductive films is opened so as to penetrate through a bonding interface thereof. The area of the contact hole penetrating through the bonding interface is not eroded by an etching solution. Thus, where manufacturing a substrate device in which a contact hole penetrating through a bonding interface needs to be formed, it is unlikely that a defect will occur in the area where the contact hole passing through the bonding interface, thereby enhancing device reliability and manufacturing yield.
    Type: Application
    Filed: March 20, 2002
    Publication date: October 10, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shigenori Katayama
  • Publication number: 20020093019
    Abstract: A channel region of a semiconductor layer has an extending portion. The terminal of the extending portion is connected to a first contact hole. The first contact hole is connected to a connecting line. The connecting line is connected to the first contact hole at one end, as described above, extends directly above a capacitor line in the Y direction, and is connected to the capacitor line via a second contact hole at this position.
    Type: Application
    Filed: March 15, 2002
    Publication date: July 18, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Shigenori Katayama, Masahiro Yasukawa
  • Patent number: 6403395
    Abstract: A channel region of a semiconductor layer has an extending portion. The terminal of the extending portion is connected to a first contact hole. The first contact hole is connected to a connecting line. The connecting line is connected to the first contact hole at one end, as described above, extends directly above a capacitor line in the Y direction, and is connected to the capacitor line via a second contact hole at this position.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: June 11, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Shigenori Katayama, Masahiro Yasukawa
  • Publication number: 20020008240
    Abstract: A channel region of a semiconductor layer has an extending portion. The terminal of the extending portion is connected to a first contact hole. The first contact hole is connected to a connecting line. The connecting line is connected to the first contact hole at one end, as described above, extends directly above a capacitor line in the Y direction, and is connected to the capacitor line via a second contact hole at this position.
    Type: Application
    Filed: August 28, 2001
    Publication date: January 24, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Shigenori Katayama, Masahiro Yasukawa
  • Patent number: 6320204
    Abstract: A channel region of a semiconductor layer has an extending portion. The terminal of the extending portion is connected to a first contact hole. The first contact hole is connected to a connecting line. The connecting line is connected to the first contact hole at one end, as described above, extends directly above a capacitor line in the Y direction, and is connected to the capacitor line via a second contact hole at this position.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: November 20, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Shigenori Katayama, Masahiro Yasukawa
  • Patent number: 6310372
    Abstract: In a conventional MOS semiconductor device of a thin film SOI structure, excessive carriers accumulated in the channel region cause some problems, such as a decreased drain breakdown voltage and formation of kink in the current-voltage relationship, resulting in malfunction. Accordingly, drainage of the excessive carriers accumulated in the semiconductor layer functioning as a channel region of the thin film transistor on a substrate for electro-optical apparatuses is achieved.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: October 30, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Shigenori Katayama, Masahiro Yasukawa
  • Patent number: 6100947
    Abstract: In a conventional reflective liquid crystal panel (liquid crystal panel) using a semiconductor substrate, since storage capacitors are formed on the surface of the substrate, with a small pixel size, a sufficient storage capacitor (50 to 100 fF) cannot be ensured, and a voltage necessary for driving a liquid crystal cannot be held. The reflective electrode of each of pixels serves as a conductive layer of one of a pair of electrodes which constitute a storage capacitor, and the other conductive layer of the storage capacitor is formed below the reflective electrode through an insulation film so that the other conductive layer is fixed at the predetermined potential.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: August 8, 2000
    Assignee: Seiko Epson Corporation
    Inventor: Shigenori Katayama
  • Patent number: 6066860
    Abstract: In a conventional MOS semiconductor device of a thin film SOI structure, excessive carriers accumulated in the channel region cause some problems, such as a decreased drain breakdown voltage and formation of kink in the current-voltage relationship, resulting in malfunction. Accordingly, drainage of the excessive carriers accumulated in the semiconductor layer functioning as a channel region of the thin film transistor on a substrate for electro-optical apparatuses is achieved.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: May 23, 2000
    Assignee: Seiko Epson Corporation
    Inventors: Shigenori Katayama, Masahiro Yasukawa