Abstract: To provide a VLC decoder having a decoding speed sufficiently high to be applicable for decoding MPEG 2 data, and having an appropriate circuit size to be integrated on an IC chip, a VLC decoder comprises: a first decode table (102) implemented with logic circuits for decoding a "zero-run code" at one clock; a second decode table (104) implemented on a memory device for decoding other VLC making use of a tree searching technique; a switching means (103, 105, 108) for switching from the first decode table (102) to the second decode table (104) when EOB code is decoded and switching from the second decode table (104) to the first decode table (102) when the "zero-run code" begins.

Abstract: A zero-run developing circuit for performing a zero-run developing process for placing zeros represented by a run between first non-zero data and second non-zero data of a block of a predetermined number of run-length signals, each of which is composed of the level of the value of non-zero data and the run that is the number of zero-data followed by the non-zero data is disclosed, that comprises a latch circuit for latching the levels of the predetermined number of the non-zero data, a first write position generating circuit for generating a first latch position of the latch circuit at which the first non-zero data is written corresponding to a first run length signal, and a second write position generating circuit for generating a second latch position of the latch circuit at which the second non-zero data is written corresponding to the first run-length signal and a second run-length signal.

Abstract: A timing signal generator of an MPEG video decoder is responsive to a picture type signal for selectively generating one of a timing signal for decoding I and P pictures and a timing signal for decoding a B picture within a predetermined period of time, permitting an increased speed for the B picture decoding.

Abstract: A Huffman code decoding circuit including a leading bit position determination unit for determining a leading bit position of a Huffman code to be taken out of a Huffman code data sequence to take in a predetermined number of bits from the leading bit position of the Huffman code data sequence, a first decoding table for inputting a first data sequence composed of a predetermined number of bits staring with the leading bit of the Huffman code data sequence output from the leading bit position determination unit to output a first decoded word and a first code length corresponding to the first data sequence input as an address, a plurality of 2nd to n-th decoding tables for inputting 2nd to n-th data sequences composed of a predetermined number of bits starting at a different bit position of the Huffman code data sequence output from the leading bit position determination unit to output a decoded word and a code length corresponding to the 2nd to n-th data sequences input as addresses, and a selector for select

Abstract: A quantization coefficient is inputted to an inverse quantization circuit. The coefficient is multiplied by a quantization step size stored in a quantization table. Resultant data is delivered to an inverse discrete cosine transformation circuit. The quantization step size is attained by replacing each value of a high-frequency portion of the quantization table with "0" by a masking circuit. As a consequence, each value of inversely quantized data associated with the portion is set to "0". Data inversely transformed according to a transformation expression is fed to a sub-sampling circuit. Based on an n specification signal, the data is sub-sampled such that a dot is extracted for every n dots, thereby generating a compressed image signal. Aliasing noise is prevented by the masking a portion of the quantization table, and the sub-sampling ratio can be varied.

Abstract: An image data coding apparatus and method to achieve a scale-down of a circuit without sacrificing compression efficiency. Input image data is delayed in a delay circuit and a coincidence detector compares the image data and delay image data to output a coincident code when these two are the same. An adaptive run length counter adaptively switches to select either a coincident code run length of a continuous length of the coincident codes calculated at an output time of the coincident codes or an image data run length of a continuous length of the same codes of the image data calculated at a non-output time of the coincident codes and outputs an adaptive run length. A Huffman coder carries out a Huffman coding of the adaptive run length.

Abstract: A huffman code decoding circuit has a memory storing a decoded word and a code length or a pointer to be accessed in the next time determined on the basis of a state transition upon decoding of a bit variable length code per every one or n bits and a flag representative of the decoding condition of the code and outputting the decoded word and the code length or the pointer for next access and the flag corresponding to an access address of m bits. A latching circuit latches the pointer of m-1 bit output from the memory when the flag is indicative of continuation of decoding, and is reset when the flag output from the memory is indicative of completion of decoding. A selector selectively outputs n-1 bit from one of the latching circuit and the bit variable length code to the memory, according to selection for decoding of the bit variable length code per every 1 bit or every n bit.