Patents by Inventor Shigenori Sawachi

Shigenori Sawachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9627289
    Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: April 18, 2017
    Assignee: J-DEVICES CORPORATION
    Inventors: Yoshihiko Ikemoto, Shigenori Sawachi, Fumihiko Taniguchi, Akio Katsumata
  • Publication number: 20160181194
    Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 23, 2016
    Inventors: Yoshihiko IKEMOTO, Shigenori SAWACHI, Fumihiko TANIGUCHI, Akio KATSUMATA
  • Patent number: 9196507
    Abstract: A method of manufacturing a semiconductor device having an insulating substrate, a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards, a first insulating material layer (A) which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto, a first metal thin film wire layer provided on the first insulating material layer (A) and a portion of which is exposed to an external surface, a first insulating material layer (B) provided on the first metal thin film wire layer, a second insulating material layer provided on a main surface of the insulating substrate where the semiconductor element is not mounted, a second metal thin film wire layer provided inside the second insulating material layer.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: November 24, 2015
    Assignee: J-DEVICES CORPORATION
    Inventors: Hiroshi Inoue, Akio Katsumata, Shigenori Sawachi, Osamu Yamagata
  • Publication number: 20150332937
    Abstract: A method of manufacturing a semiconductor device having an insulating substrate, a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards, a first insulating material layer (A) which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto, a first metal thin film wire layer provided on the first insulating material layer (A) and a portion of which is exposed to an external surface, a first insulating material layer (B) provided on the first metal thin film wire layer, a second insulating material layer provided on a main surface of the insulating substrate where the semiconductor element is not mounted, a second metal thin film wire layer provided inside the second insulating material layer.
    Type: Application
    Filed: July 23, 2015
    Publication date: November 19, 2015
    Inventors: Hiroshi INOUE, Akio KATSUMATA, Shigenori SAWACHI, Osamu YAMAGATA
  • Patent number: 9147671
    Abstract: A semiconductor device, having an insulating substrate; a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards; a first insulating material layer which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto; a first metal thin film wire layer which is provided on the first insulating material layer (A) and a portion of which is exposed to an external surface; a first insulating material layer (B) which is provided on the first metal thin film wire layer; a second insulating material layer which is provided on a main surface of the insulating substrate where the semiconductor element is not mounted; and a second metal thin film wire layer which is provided inside the second insulating material layer.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: September 29, 2015
    Assignee: J-DEVICES CORPORATION
    Inventors: Hiroshi Inoue, Akio Katsumata, Shigenori Sawachi, Osamu Yamagata
  • Publication number: 20150243632
    Abstract: A semiconductor device, having an insulating substrate; a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards; a first insulating material layer which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto; a first metal thin film wire layer which is provided on the first insulating material layer (A) and a portion of which is exposed to an external surface; a first insulating material layer (B) which is provided on the first metal thin film wire layer; a second insulating material layer which is provided on a main surface of the insulating substrate where the semiconductor element is not mounted; and a second metal thin film wire layer which is provided inside the second insulating material layer.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Inventors: Hiroshi INOUE, Akio KATSUMATA, Shigenori SAWACHI, Osamu YAMAGATA
  • Patent number: 8872350
    Abstract: A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 28, 2014
    Assignee: J-Devices Corporation
    Inventors: Shigenori Sawachi, Osamu Yamagata, Hiroshi Inoue, Satoru Itakura, Tomoshige Chikai, Masahiko Hori, Akio Katsumata
  • Patent number: 8618657
    Abstract: A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiichiro Higaki, Koichi Sugihara, Katsuya Murakami, Shigenori Sawachi, Mitsuru Oida
  • Publication number: 20130200523
    Abstract: A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.
    Type: Application
    Filed: September 14, 2012
    Publication date: August 8, 2013
    Inventors: Shigenori SAWACHI, Osamu Yamagata, Hiroshi Inoue, Satoru Itakura, Tomoshige Chikai, Masahiko Hori, Akio Katsumata
  • Publication number: 20130026650
    Abstract: A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 31, 2013
    Inventors: Osamu Yamagata, Akio Katsumata, Hiroshi Inoue, Shigenori Sawachi, Satoru Itakura, Yasuhiro Yamaji
  • Publication number: 20100213599
    Abstract: A semiconductor device includes: a flat plate; a semiconductor chip which is disposed on one main surface of the flat plate and whose surface opposite an element circuit surface is fixedly bonded; a single layer of an insulating material layer formed continuously on the element circuit surface of the semiconductor chip and on the main surface of the flat plate; an opening formed at a position, in the insulating material layer, above an electrode disposed on the element circuit surface of the semiconductor chip; a conductive part formed in the opening so as to be connected to the electrode of the semiconductor chip; a wiring layer formed on the insulating material layer so as to be connected to the conductive part, and partly led out to a peripheral area of the semiconductor chip; and external electrodes formed on the wiring layer.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 26, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro Watanabe, Seiki Takata, Toshitsune Iijima, Tomomi Sato, Shigenori Sawachi, Takumi Kawana, Osamu Yamagata, Hiroshi Nomura, Yumiko Oshima
  • Publication number: 20100032833
    Abstract: A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 11, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiichiro Higaki, Koichi Sugihara, Katsuya Murakami, Shigenori Sawachi, Mitsuru Oida