Patents by Inventor Shigenori Sawachi
Shigenori Sawachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9627289Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.Type: GrantFiled: December 9, 2015Date of Patent: April 18, 2017Assignee: J-DEVICES CORPORATIONInventors: Yoshihiko Ikemoto, Shigenori Sawachi, Fumihiko Taniguchi, Akio Katsumata
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Publication number: 20160181194Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.Type: ApplicationFiled: December 9, 2015Publication date: June 23, 2016Inventors: Yoshihiko IKEMOTO, Shigenori SAWACHI, Fumihiko TANIGUCHI, Akio KATSUMATA
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Patent number: 9196507Abstract: A method of manufacturing a semiconductor device having an insulating substrate, a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards, a first insulating material layer (A) which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto, a first metal thin film wire layer provided on the first insulating material layer (A) and a portion of which is exposed to an external surface, a first insulating material layer (B) provided on the first metal thin film wire layer, a second insulating material layer provided on a main surface of the insulating substrate where the semiconductor element is not mounted, a second metal thin film wire layer provided inside the second insulating material layer.Type: GrantFiled: July 23, 2015Date of Patent: November 24, 2015Assignee: J-DEVICES CORPORATIONInventors: Hiroshi Inoue, Akio Katsumata, Shigenori Sawachi, Osamu Yamagata
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Publication number: 20150332937Abstract: A method of manufacturing a semiconductor device having an insulating substrate, a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards, a first insulating material layer (A) which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto, a first metal thin film wire layer provided on the first insulating material layer (A) and a portion of which is exposed to an external surface, a first insulating material layer (B) provided on the first metal thin film wire layer, a second insulating material layer provided on a main surface of the insulating substrate where the semiconductor element is not mounted, a second metal thin film wire layer provided inside the second insulating material layer.Type: ApplicationFiled: July 23, 2015Publication date: November 19, 2015Inventors: Hiroshi INOUE, Akio KATSUMATA, Shigenori SAWACHI, Osamu YAMAGATA
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Patent number: 9147671Abstract: A semiconductor device, having an insulating substrate; a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards; a first insulating material layer which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto; a first metal thin film wire layer which is provided on the first insulating material layer (A) and a portion of which is exposed to an external surface; a first insulating material layer (B) which is provided on the first metal thin film wire layer; a second insulating material layer which is provided on a main surface of the insulating substrate where the semiconductor element is not mounted; and a second metal thin film wire layer which is provided inside the second insulating material layer.Type: GrantFiled: February 26, 2014Date of Patent: September 29, 2015Assignee: J-DEVICES CORPORATIONInventors: Hiroshi Inoue, Akio Katsumata, Shigenori Sawachi, Osamu Yamagata
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Publication number: 20150243632Abstract: A semiconductor device, having an insulating substrate; a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards; a first insulating material layer which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto; a first metal thin film wire layer which is provided on the first insulating material layer (A) and a portion of which is exposed to an external surface; a first insulating material layer (B) which is provided on the first metal thin film wire layer; a second insulating material layer which is provided on a main surface of the insulating substrate where the semiconductor element is not mounted; and a second metal thin film wire layer which is provided inside the second insulating material layer.Type: ApplicationFiled: February 26, 2014Publication date: August 27, 2015Inventors: Hiroshi INOUE, Akio KATSUMATA, Shigenori SAWACHI, Osamu YAMAGATA
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Patent number: 8872350Abstract: A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.Type: GrantFiled: September 14, 2012Date of Patent: October 28, 2014Assignee: J-Devices CorporationInventors: Shigenori Sawachi, Osamu Yamagata, Hiroshi Inoue, Satoru Itakura, Tomoshige Chikai, Masahiko Hori, Akio Katsumata
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Patent number: 8618657Abstract: A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.Type: GrantFiled: August 5, 2009Date of Patent: December 31, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kiichiro Higaki, Koichi Sugihara, Katsuya Murakami, Shigenori Sawachi, Mitsuru Oida
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Publication number: 20130200523Abstract: A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.Type: ApplicationFiled: September 14, 2012Publication date: August 8, 2013Inventors: Shigenori SAWACHI, Osamu Yamagata, Hiroshi Inoue, Satoru Itakura, Tomoshige Chikai, Masahiko Hori, Akio Katsumata
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Publication number: 20130026650Abstract: A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.Type: ApplicationFiled: July 24, 2012Publication date: January 31, 2013Inventors: Osamu Yamagata, Akio Katsumata, Hiroshi Inoue, Shigenori Sawachi, Satoru Itakura, Yasuhiro Yamaji
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Publication number: 20100213599Abstract: A semiconductor device includes: a flat plate; a semiconductor chip which is disposed on one main surface of the flat plate and whose surface opposite an element circuit surface is fixedly bonded; a single layer of an insulating material layer formed continuously on the element circuit surface of the semiconductor chip and on the main surface of the flat plate; an opening formed at a position, in the insulating material layer, above an electrode disposed on the element circuit surface of the semiconductor chip; a conductive part formed in the opening so as to be connected to the electrode of the semiconductor chip; a wiring layer formed on the insulating material layer so as to be connected to the conductive part, and partly led out to a peripheral area of the semiconductor chip; and external electrodes formed on the wiring layer.Type: ApplicationFiled: February 11, 2010Publication date: August 26, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Watanabe, Seiki Takata, Toshitsune Iijima, Tomomi Sato, Shigenori Sawachi, Takumi Kawana, Osamu Yamagata, Hiroshi Nomura, Yumiko Oshima
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Publication number: 20100032833Abstract: A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.Type: ApplicationFiled: August 5, 2009Publication date: February 11, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kiichiro Higaki, Koichi Sugihara, Katsuya Murakami, Shigenori Sawachi, Mitsuru Oida