Patents by Inventor Shigenori Yamashita

Shigenori Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11926931
    Abstract: A resin powder for solid freeform fabrication includes a particle having a pillar-like form, wherein the ratio of the height of the particle to the diameter or the long side of the bottom of the particle is 0.5 to 2.0, the particle has a 50 percent cumulative volume particle diameter of from 5 to 200 ?m, and the ratio (Mv/Mn) of the volume average particle diameter (Mv) to the number average particle diameter (Mn) of the particle is 2.00 or less.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: March 12, 2024
    Assignee: Ricoh Company, Ltd.
    Inventors: Akira Saito, Shigenori Yaguchi, Yasuyuki Yamashita, Kiichi Kamoda, Yasuo Suzuki, Nozomu Tamoto, Hitoshi Iwatsuki, Shinzo Higuchi, Sohichiroh Iida
  • Patent number: 8043772
    Abstract: In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at a past time are measured. A resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of the measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of the estimated resist dimension and focus position. Then, an exposure dose is calculated with considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using the calculated exposure dose and focus offset value.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiharu Miwa, Junko Konishi, Toshihide Kawachi, Shigenori Yamashita, Takeshi Tashiro, Hidekimi Fudo
  • Publication number: 20090286174
    Abstract: In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at past time are measured, a resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of these measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of these estimated resist dimension and focus position, and then, an exposure dose is calculated as considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using these calculated exposure dose and focus offset value.
    Type: Application
    Filed: May 15, 2009
    Publication date: November 19, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Toshiharu MIWA, Junko KONISHI, Toshihide KAWACHI, Shigenori YAMASHITA, Takeshi TASHIRO, Hidekimi FUDO
  • Patent number: 6617080
    Abstract: The present invention provides a photomask, a semiconductor device, and a method for exposing through the photomask. The photomask comprises a photomask substrate, and an on-mask circuit area including an on-mask circuit pattern and an on-mask test mark area including an on-mask test pattern, both formed on the surface of the substrate, wherein the photomask substrate further includes an on-mask photolithography screening mark area including an on-mask comparison pattern and an on-mask screening pattern, the on-mask comparison pattern has substantially the same configuration as at least a part of the on-mask circuit pattern, and the on-mask screening pattern has substantially the same configuration as at least a part of the on-mask test pattern. The present invention allows it to measure the actual displacement generated from an overlaying (i.e. alignment) process for the purpose of eliminating of an the overlay displacement which can take place in a photolithography process.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: September 9, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihide Kawachi, Takuya Matsushita, Shigenori Yamashita, Yuki Miyamoto, Atsushi Ueno, Shinroku Maejima
  • Patent number: 6323560
    Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: November 27, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koichiro Narimatsu, Shigenori Yamashita, Nobuyuki Yoshioka, Shinya Soeda, Atsushi Hachisuka, Koji Taniguchi, Yuki Miyamoto, Takayuki Saito, Ayumi Minamide
  • Patent number: 6068952
    Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: May 30, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koichiro Narimatsu, Shigenori Yamashita, Nobuyuki Yoshioka, Shinya Soeda, Atsushi Hachisuka, Koji Taniguchi, Yuki Miyamoto, Takayuki Saito, Ayumi Minamide
  • Patent number: 5892291
    Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: April 6, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koichiro Narimatsu, Shigenori Yamashita, Nobuyuki Yoshioka, Shinya Soeda, Atsushi Hachisuka, Koji Taniguchi, Yuki Miyamoto, Takayuki Saito, Ayumi Minamide
  • Patent number: 5830607
    Abstract: A second light transmit portion of a phase shift mask is formed of a molybdenum silicide nitride oxide, or a molybdenum silicide oxide, or a chromium nitride oxide, or a chromium oxide, or a chromium carbide nitride oxide film converting a phase of transmitted exposure light by 180.degree. and having the transmittance of at least 2% and less than 5%. In the manufacturing method of the second light transmit portion, a molybdenum silicide nitride oxide film, or a molybdenum silicide oxide film, or a chromium nitride oxide film, or a chromium oxide film, or a carbide nitride oxide film is formed by a sputtering method. Consequently, with a conventional sputtering apparatus, the second light transmit portion can be formed, and additionally, etching process of the phase shifter portion is required only once, so that probabilities of defects and errors in the manufacturing process can be decreased.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: November 3, 1998
    Assignees: Ulvac Coating Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihiko Isao, Ryoichi Kobayashi, Nobuyuki Yoshioka, Yaichiro Watakabe, Junji Miyazaki, Kouichiro Narimatsu, Shigenori Yamashita
  • Patent number: 5674647
    Abstract: A second light transmit portion of a phase shift mask is formed of a molybdenum silicide nitride oxide, or a molybdenum silicide oxide, or a chromium nitride oxide, or a chromium oxide, or a chromium carbide nitride oxide film converting a phase of transmitted exposure light by 180.degree. and having the transmittance of at least 2% and less than 5%. In the manufacturing method of the second light transmit portion, a molybdenum silicide nitride oxide film, or a molybdenum silicide oxide film, or a chromium nitride oxide film, or a chromium oxide film, or a carbide nitride oxide film is formed by a sputtering method. Consequently, with a conventional sputtering apparatus, the second light transmit portion can be formed, and additionally, etching process of the phase shifter portion is required only once, so that probabilities of defects and errors in the manufacturing process can be decreased.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: October 7, 1997
    Assignees: Ulvac Coating Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihiko Isao, Ryoichi Kobayashi, Nobuyuki Yoshioka, Yaichiro Watakabe, Junji Miyazaki, Kouichiro Narimatsu, Shigenori Yamashita