Abstract: That surface of an electrode plate 20 which is opposite to a susceptor 10 has a projection shape. The electrode plate 20 is fitted in an opening 26a of shield ring 26 at a projection 20a. At this time, the thickness of the projection 20a is approximately the same as the thickness of the shield ring 26. Accordingly, the electrode plate 20 and the shield ring 26 form substantially the same plane. The major surface of the projection 20a has a diameter 1.2 to 1.5 times the diameter of a wafer W. The electrode plate 20 is formed of, for example, SiC.

Abstract: The present invention is a method of manufacturing a semiconductor device from a layered body including: a semiconductor substrate; a high dielectric film formed on the semiconductor substrate; and an SiC-based film formed on a position upper than the high dielectric film, the SiC-based film having an anti-reflective function and a hardmask function. The present invention comprises a plasma-processing step for plasma-processing the SiC-based film and the high dielectric film to modify the SiC-based film and the high dielectric film by an action of a plasma; and a cleaning step for wet-cleaning the SiC-based film and the high dielectric film modified in the plasma-processing step to collectively remove the SiC-based film and the high dielectric film.

Abstract: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.

Abstract: The present invention is a method of manufacturing a semiconductor device from a layered body including: a semiconductor substrate; a high dielectric film formed on the semiconductor substrate; and an SiC-based film formed on a position upper than the high dielectric film, the SiC-based film having an anti-reflective function and a hardmask function. The present invention comprises a plasma-processing step for plasma-processing the SiC-based film and the high dielectric film to modify the SiC-based film and the high dielectric film by an action of a plasma; and a cleaning step for wet-cleaning the SiC-based film and the high dielectric film modified in the plasma-processing step to collectively remove the SiC-based film and the high dielectric film.

Abstract: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.

Abstract: A processing method of a substrate includes: a step of forming an Si—C based film and a resist film in turn on an objective film to be etched that has been formed on a substrate; a first etching step of etching the Si—C based film making use of the resist film as a mask; and a second etching step of etching the objective film to be etched making use of the resist film and the Si—C based film as a mask. The processing method further includes a peeling-off step of peeling-off the resist film at a desired timing. The peeling-off step includes a preparing step of preparing an organic solvent as a release agent, and an applying step of applying the organic solvent to the resist film.

Abstract: In a parallel plate type plasma processing apparatus (1), a baffle plate (28) is fitted between a ceiling (2b) and side wall (2a) of a chamber (2). The baffle plate (28) confines plasma into the upper portion of the chamber (2), and at the same time, constitutes a return route of a return current to a high frequency power source (27). A return current flowing through the baffle plate (28) returns to the high frequency power source (27) via the ceiling (2b) of the chamber (2).

Abstract: That surface of an electrode plate 20 which is opposite to a susceptor 10 has a projection shape. The electrode plate 20 is fitted in an opening 26a of shield ring 26 at a projection 20a. At this time, die thickness of the projection 20a is approximately the same as the thickness of the shield ring 26. Accordingly, the electrode plate 20 and the shield ring 26 form substantially the same plane. The major surface of the projection 20a has a diameter 1.2 to 1.5 times the diameter of a wafer W. The electrode plate 20 is formed of, for example, SiC.

Abstract: In a parallel plate type plasma processing apparatus (1), a baffle plate (28) is fitted between a ceiling (2b) and side wall (2a) of a chamber (2). The baffle plate (28) confines plasma into the upper portion of the chamber (2), and at the same time, constitutes a return route of a return current to a high frequency power source (27). A return current flowing through the baffle plate (28) returns to the high frequency power source (27) via the ceiling (2b) of the chamber (2).

Abstract: That surface of an electrode plate 20 which is opposite to a susceptor 10 has a projection shape. The electrode plate 20 is fitted in an opening 26a of shield ring 26 at a projection 20a. At this time, the thickness of the projection 20a is approximately the same as the thickness of the shield ring 26. Accordingly, the electrode plate 20 and the shield ring 26 form substantially the same plane. The major surface of the projection 20a has a diameter 1.2 to 1.5 times the diameter of a wafer W. The electrode plate 20 is formed of, for example, SiC.

Abstract: A fuse link 16 is formed of a portion of a top level of patterned metal conductor in a multilevel conductor integrated circuit 10. A deposited layer of oxide material 26 covers the fuse link. Radiant energy from such as a laser 36 is directed through the oxide material 26 to heat and open the fuse link 16. Layers of deposited protective oxide 28 and PIX 30 then cover the fuse link and layer of oxide material. One photoprocessing step is avoided by locating the fuse link 16 and bond pad 22, both made from the top layer of conductive material, at different levels. The blanket etch then exposes the bond pad 22 while leaving the fuse link 16 covered. The fuse link can be formed down in a step 38 or the bond pad 22 can be formed above such as a group of memory cells 80. The bond pad 22 and fuse link 16 also can be formed at the same level with other process procedures.

Abstract: A manufacturing method for semiconductor devices such as dynamic RAM, etc. which removes the layer part more on the high position than an arbitrary position on a step forming a gradation by just a prescribed thickness when flattening a layer with a gradation formed of a high position part and a low position part. Then the projecting part created after the etching existing more on the low position side than at the arbitrary position of the gradation is eliminated by heat treatment.

Abstract: A semiconductor manufacturing method for devices, such as a DRAM, having a plurality of circuit elements of at least two substantially different heights (such as memory-cells vs. peripheral circuits) on a common semiconductor substrate. A plurality of circuit elements of at least two substantially different heights are formed on a common semiconductor substrate. A common insulating layer, such as BPSG, whose top surface has substantial variation in height above the substrate, is deposited over the circuit elements. A resist mask layer is deposited over the insulating layer with openings over high portions of the insulating layer's top surface exceeding a first predetermined height. Then the insulating layer's high portions are etched down to a second predetermined height to make its overall top surface more even, and the resist mask layer removed. The enables a working layer that would be easily damaged by substantial height variation to be deposited on the evened insulating layer.

Abstract: A fuse link 16 is formed of a portion of a top level of patterned metal conductor in a multilevel conductor integrated circuit 10. A deposited layer of oxide material 26 covers the fuse link. Radiant energy from such as a laser 36 is directed through the oxide material 26 to heat and open the fuse link 16. Layers of deposited protective oxide 28 and PIX 30 then cover the fuse link and layer of oxide material. One photoprocessing step is avoided by locating the fuse link 16 and bond pad 22, both made from the top layer of conductive material, at different levels. The blanket etch then exposes the bond pad 22 while leaving the fuse link 16 covered. The fuse link can be formed down in a step 38 or the bond pad 22 can be formed above such as a group of memory cells 80. The bond pad 22 and fuse link 16 also can be formed at the same level with other process procedures.