Abstract: A semiconductor device and a semiconductor device manufacturing method provide a self align contact hole which is easy to restrain deterioration of insulation characteristics between an upper wiring layer connecting to a lower wiring layer via a self matching self align contact hole for a middle wiring layer and a middle wiring layer. The side of a bit contact hole which is self matching for a gate electrode is directly covered with a silicon oxide film spacer and a silicon oxide film spacer is reflowed and covered with a BPSG film spacer. With these processes, the restraint of the deterioration of insulation characteristics is implemented.

Abstract: A semiconductor device and a semiconductor device manufacturing method provide a self align contact hole which is easy to restrain deterioration of insulation characteristics between an upper wiring layer connecting to a lower wiring layer via a self matching self align contact hole for a middle wiring layer and a middle wiring layer. The side of a bit contact hole which is self matching for a gate electrode is directly covered with a silicon oxide film spacer and a silicon oxide film spacer is reflowed and covered with a BPSG film spacer. With these processes, the restraint of the deterioration of insulation characteristics is implemented.

Abstract: An output driver is implemented by a complementary inverter circuit responsive to an output data signal for selectively charging and discharging an external capacitive load, and the complementary inverter circuit has a p-channel enhancement type field effect transistor formed in an n-type well defined in a p-type silicon substrate reversely biased and an n-channel enhancement type field effect transistor formed in a p-type well nested with a reversely biased n-type well defined in the p-type silicon substrate in spacing relation to the n-type well assigned to the p-channel enhancement type field effect transistor, thereby perfectly isolating the p-channel enhancement type field effect transistor from a noise propagated from a ground voltage line to the p-type well assigned to the n-channel enhancement type field effect transistor.

Abstract: A semiconductor memory device includes at least one word line, at least one memory cell coupled to the word line, a decoder circuit responding to address information to generate a word line drive signal taking one of an active level and an inactive level, a signal generator generating a reset signal tacking an active level in a reset mode and an inactive level in a selection mode, and a word line driver coupled to receive the word line drive signal and the reset signal and to the word line. The word line driver includes a first drive circuit responding to the active level of the reset signal to drive the word line to a non-selection level and maintaining the word line at the non-selection level when the word line drive signal and the reset signal are at the inactive level. A second drive circuit responds to the active level of the word line drive signal and the inactive level of the reset signal to drive the word line to a selection level.

Abstract: A memory cell array is divided into a plurality of blocks selected by an upper row address and further divided into a plurality of sub blocks in a word line direction. Word line driving circuits are provided individually for each of the sub blocks. Further, a plurality of word line driving current supplying circuits are provided which are selectively activated in response to an input of all or part of an upper row address for selection of one of the plurality of blocks to supply word line driving current to the word line driving circuits. The word line driving circuits in the same column direction are supplied with word line driving current by way of at least two signal lines.

Abstract: A semiconductor memory device improves the power source margin without having an extended chip area. The semiconductor memory device of the present invention has a plurality of divided word lines, each having a plurality of drivers for supplying an electric current. The semiconductor memory device includes a boosting circuit for boosting and then supplying an external voltage to the plurality of drivers, and a voltage detection circuit for outputting detection signals which show the results of a comparison made between outputs of the boosting circuit and a reference voltage. The boosting circuit is structured so as to boost the external voltage according to the results of the comparison shown by the detection signals.