Patents by Inventor Shigeo CHIYODA

Shigeo CHIYODA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9842038
    Abstract: Embodiments of the present invention utilize a dual buffer size threshold system for raising interrupts that allows DUT testing systems to perform real-time buffer memory allocation procedures in an on demand basis. Using dual interrupt threshold systems in the manner described by embodiments of the present invention, DUT testing systems can reduce the need to decide on a single buffer size threshold when testing a set of DUTs that separately provide different amounts of fail data relative to each other. As such, embodiments of the present invention can minimize the overhead processing spent on interrupt handling while also reducing the amount wait time needed for the data processing module to process fail data for each DUT. Thus, embodiments of the present invention can increase the use of tester resources more efficiently while decrease the amount of time a tester system spends collecting and/or analyzing fail data for a set of DUTs during a testing session.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 12, 2017
    Assignee: Advantest Corporation
    Inventors: Xinguo Zhang, Yi Liu, Ze'ev Raz, Darrin Albers, Alan S. Krech, Jr., Shigeo Chiyoda, Jesse Hobbs
  • Publication number: 20160321153
    Abstract: Embodiments of the present invention utilize a dual buffer size threshold system for raising interrupts that allows DUT testing systems to perform real-time buffer memory allocation procedures in an on demand basis. Using dual interrupt threshold systems in the manner described by embodiments of the present invention, DUT testing systems can reduce the need to decide on a single buffer size threshold when testing a set of DUTs that separately provide different amounts of fail data relative to each other. As such, embodiments of the present invention can minimize the overhead processing spent on interrupt handling while also reducing the amount wait time needed for the data processing module to process fail data for each DUT. Thus, embodiments of the present invention can increase the use of tester resources more efficiently while decrease the amount of time a tester system spends collecting and/or analyzing fail data for a set of DUTs during a testing session.
    Type: Application
    Filed: April 30, 2015
    Publication date: November 3, 2016
    Inventors: Xinguo ZHANG, Yi LIU, Ze'ev RAZ, Darrin ALBERS, Alan S. KRECH, JR., Shigeo CHIYODA, Jesse HOBBS