Patents by Inventor Shigeo Homma
Shigeo Homma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11698857Abstract: A storage system monitors the first access frequency of occurrence which is the access frequency of occurrence from a host device during a first period, and the second access frequency of occurrence which is the access frequency of occurrence from a host device during a second period shorter than the first period. Along with performing data relocation among the tiers (levels) in the first period cycle based on the first access frequency of occurrence, the storage system performs a decision whether or not to perform a second relocation based on the first access frequency of occurrence and the second access frequency of occurrence, synchronously with access from a host device. Here the threshold value utilized in a decision on whether or not to perform the first relocation is different from the threshold value utilized in a decision on whether or not to perform the second relocation.Type: GrantFiled: June 24, 2022Date of Patent: July 11, 2023Assignee: HITACHI, LTD.Inventors: Hiroaki Akutsu, Akira Yamamoto, Shigeo Homma, Masanobu Yamamoto, Yoshinori Ohira
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Publication number: 20220318134Abstract: A storage system monitors the first access frequency of occurrence which is the access frequency of occurrence from a host device during a first period, and the second access frequency of occurrence which is the access frequency of occurrence from a host device during a second period shorter than the first period. Along with performing data relocation among the tiers (levels) in the first period cycle based on the first access frequency of occurrence, the storage system performs a decision whether or not to perform a second relocation based on the first access frequency of occurrence and the second access frequency of occurrence, synchronously with access from a host device. Here the threshold value utilized in a decision on whether or not to perform the first relocation is different from the threshold value utilized in a decision on whether or not to perform the second relocation.Type: ApplicationFiled: June 24, 2022Publication date: October 6, 2022Inventors: Hiroaki AKUTSU, Akira YAMAMOTO, Shigeo HOMMA, Masanobu YAMAMOTO, Yoshinori OHIRA
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Patent number: 11372755Abstract: A storage system monitors the first access frequency of occurrence which is the access frequency of occurrence from a host device during a first period, and the second access frequency of occurrence which is the access frequency of occurrence from a host device during a second period shorter than the first period. Along with performing data relocation among the tiers (levels) in the first period cycle based on the first access frequency of occurrence, the storage system performs a decision whether or not to perform a second relocation based on the first access frequency of occurrence and the second access frequency of occurrence, synchronously with access from a host device. Here the threshold value utilized in a decision on whether or not to perform the first relocation is different from the threshold value utilized in a decision on whether or not to perform the second relocation.Type: GrantFiled: July 17, 2020Date of Patent: June 28, 2022Assignee: HITACHI, LTD.Inventors: Hiroaki Akutsu, Akira Yamamoto, Shigeo Homma, Masanobu Yamamoto, Yoshinori Ohira
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Patent number: 11210214Abstract: A storage system including a storage controller for compressing a data from a host and a plurality of nonvolatile memory drives for writing the compressed data. The storage controller provides the host with a first logical address space as a logical storage area and includes a plurality of first physical address spaces corresponding to the first logical address space and manages storage areas of the plurality of nonvolatile memory drives. Each of the plurality of nonvolatile memory drives includes a second physical address space that manages a physical storage area of the nonvolatile memory and a second logical address space that corresponds to the second physical address space and to each of the plurality of first physical address spaces. The second logical address spaces and the first logical address space are managed with a common size and a common management size, and leading addresses are aligned with the management size.Type: GrantFiled: September 13, 2019Date of Patent: December 28, 2021Assignees: HITACHI, LTD., HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING LTD.Inventors: Junji Ogawa, Shigeo Homma
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Patent number: 10915441Abstract: An upper system of an NVM device transmits, to the NVM device, a write command that designates a logical address, the write command being associated with an expiration date corresponding to a data expiration date correlated with write target data. The NVM device correlates an expiration date correlated with the write command with a logical address specified from the write command. The NVM device writes pieces of data of which the remaining time which is the time to an expiration date belongs to the same remaining time range to the same physical storage area among the plurality of physical storage areas. The NVM device erases data from a physical storage area when the expiration dates of all pieces of data in the physical storage area have expired.Type: GrantFiled: August 23, 2017Date of Patent: February 9, 2021Assignees: HITACHI, LTD., HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING LTD.Inventors: Koshi Hoshino, Shigeo Homma, Junji Ogawa, Yoshinori Ohira
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Patent number: 10838855Abstract: This storage system has one or more non-volatile memory devices and a processor unit that comprises one or more processors connected to the one or more non-volatile memory devices. At least a portion of the non-volatile memory of each of the one or more non-volatile memory devices comprises a user area, which is a storage area to which data is written, and an update area, which is a storage area to which update data for the original data is written. The processor unit changes the user capacity, namely the capacity of the user area, of each of the one or more non-volatile memory devices on the basis of at least one of one or more resource usage rates of the one or more non-volatile memory devices.Type: GrantFiled: February 20, 2017Date of Patent: November 17, 2020Assignee: HITACHI, LTD.Inventors: Naoya Machida, Shigeo Homma
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Publication number: 20200356471Abstract: A storage system monitors the first access frequency of occurrence which is the access frequency of occurrence from a host device during a first period, and the second access frequency of occurrence which is the access frequency of occurrence from a host device during a second period shorter than the first period. Along with performing data relocation among the tiers (levels) in the first period cycle based on the first access frequency of occurrence, the storage system performs a decision whether or not to perform a second relocation based on the first access frequency of occurrence and the second access frequency of occurrence, synchronously with access from a host device. Here the threshold value utilized in a decision on whether or not to perform the first relocation is different from the threshold value utilized in a decision on whether or not to perform the second relocation.Type: ApplicationFiled: July 17, 2020Publication date: November 12, 2020Inventors: Hiroaki AKUTSU, Akira YAMAMOTO, Shigeo HOMMA, Masanobu YAMAMOTO, Yoshinori OHIRA
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Publication number: 20200264971Abstract: A storage system including a storage controller for compressing a data from a host and a plurality of nonvolatile memory drives for writing the compressed data. The storage controller provides the host with a first logical address space as a logical storage area and includes a plurality of first physical address spaces corresponding to the first logical address space and manages storage areas of the plurality of nonvolatile memory drives. Each of the plurality of nonvolatile memory drives includes a second physical address space that manages a physical storage area of the nonvolatile memory and a second logical address space that corresponds to the second physical address space and to each of the plurality of first physical address spaces. The second logical address spaces and the first logical address space are managed with a common size and a common management size, and leading addresses are aligned with the management size.Type: ApplicationFiled: September 13, 2019Publication date: August 20, 2020Applicants: HITACHI, LTD., HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING, LTD.Inventors: Junji OGAWA, Shigeo HOMMA
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Patent number: 10733092Abstract: A storage system monitors the first access frequency of occurrence which is the access frequency of occurrence from a host device during a first period, and the second access frequency of occurrence which is the access frequency of occurrence from a host device during a second period shorter than the first period. Along with performing data relocation among the tiers (levels) in the first period cycle based on the first access frequency of occurrence, the storage system performs a decision whether or not to perform a second relocation based on the first access frequency of occurrence and the second access frequency of occurrence, synchronously with access from a host device. Here the threshold value utilized in a decision on whether or not to perform the first relocation is different from the threshold value utilized in a decision on whether or not to perform the second relocation.Type: GrantFiled: November 8, 2017Date of Patent: August 4, 2020Assignee: HITACHI, LTD.Inventors: Hiroaki Akutsu, Akira Yamamoto, Shigeo Homma, Masanobu Yamamoto, Yoshinori Ohira
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Patent number: 10684785Abstract: A storage system according to one aspect of the present invention includes a plurality of storage devices using flash memory as a storage medium. The flash memory used for the storage device may include flash memory configured to operate each cell as a cell capable of storing n-bit information or a cell capable of storing m-bit information (where n<m). The storage system may periodically acquire a number of remaining erasures from the storage device and predict the lifetime of the storage device by using the acquired number of remaining erasures and the storage device operation time. If the predicted lifetime is less than a predetermined value (service life) a predetermined number of cells may be changed to cells capable of storing n-bit information.Type: GrantFiled: February 23, 2017Date of Patent: June 16, 2020Assignee: Hitachi, Ltd.Inventors: Yoshihiko Fujii, Shigeo Homma, Junji Ogawa, Yoshinori Ohira
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Publication number: 20200097396Abstract: An upper system of an NVM device transmits, to the NVM device, a write command that designates a logical address, the write command being associated with an expiration date corresponding to a data expiration date correlated with write target data. The NVM device correlates an expiration date correlated with the write command with a logical address specified from the write command. The NVM device writes pieces of data of which the remaining time which is the time to an expiration date belongs to the same remaining time range to the same physical storage area among the plurality of physical storage areas. The NVM device erases data from a physical storage area when the expiration dates of all pieces of data in the physical storage area have expired.Type: ApplicationFiled: August 23, 2017Publication date: March 26, 2020Applicants: HITACHI, LTD., HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING, LTD.Inventors: Koshi HOSHINO, Shigeo HOMMA, Junji OGAWA, Yoshinori OHIRA
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Patent number: 10459639Abstract: A storage unit according to one aspect of the present invention comprises a storage controller and a plurality of storage devices. Each storage device has nonvolatile semiconductor memories serving as storage media. The controller of each storage device diagnoses the state of degradation of the nonvolatile semiconductor memories, and if one of the nonvolatile semiconductor memories is expected to be nearing end of life, then the controller copies the data stored in that degraded nonvolatile semiconductor memory to another nonvolatile semiconductor memory, and then performs shutdown processing for the degraded nonvolatile semiconductor memory, as well as storage capacity reduction processing.Type: GrantFiled: April 28, 2015Date of Patent: October 29, 2019Assignee: HITACHI, LTD.Inventors: Hideyuki Koseki, Shigeo Homma
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Patent number: 10394662Abstract: A source remote copy configuration in a source storage system is migrated to a destination storage system as a destination remote copy configuration. The destination primary storage apparatus of the destination storage system defines a virtual volume mapped to the primary volume provided by the source primary storage apparatus which is a storage area of the virtual volume; takes over a first identifier of the primary volume to the virtual volume; transfers, when the virtual volume receives an access request, the access request to the source primary storage apparatus to write data in the primary volume; and takes over the first identifier from the virtual volume to another primary volume provided by the destination primary storage apparatus, after completion of copy of data from primary volume of the source primary storage apparatus into primary volume of the destination primary storage apparatus and secondary volume of the destination secondary storage apparatus.Type: GrantFiled: December 1, 2017Date of Patent: August 27, 2019Assignee: Hitachi, Ltd.Inventors: Taiki Kono, Hidenori Suzuki, Kunihiko Nashimoto, Shigeo Homma, Toru Suzuki, Tomohiro Kawaguchi, Hideo Saito, Azusa Jin, Hiroshi Nasu, Keishi Tamura, Shoji Sugino
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Patent number: 10387062Abstract: A storage system according to one aspect of the present invention includes a plurality of storage devices using flash memory as a storage medium. The flash memory used for the storage device may include flash memory configured to operate each cell as a cell capable of storing n-bit information or a cell capable of storing m-bit information (where n<m), where n=2 and m=3. The storage system may periodically acquire a number of remaining erasures from the storage device and predict the lifetime of the storage device by using the acquired number of remaining erasures and the storage device operation time. If the predicted lifetime is greater than a predetermined value (service life), a predetermined number of cells may be changed to cells capable of storing m-bit information.Type: GrantFiled: November 27, 2015Date of Patent: August 20, 2019Assignee: HITACHI, LTD.Inventors: Tomotaro Doi, Shigeo Homma, Kenta Ninose
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Publication number: 20190205054Abstract: A storage system according to one aspect of the present invention includes a plurality of storage devices using flash memory as a storage medium. The flash memory used for the storage device may include flash memory configured to operate each cell as a cell capable of storing n-bit information or a cell capable of storing m-bit information (where n<m). The storage system may periodically acquire a number of remaining erasures from the storage device and predict the lifetime of the storage device by using the acquired number of remaining erasures and the storage device operation time. If the predicted lifetime is less than a predetermined value (service life) a predetermined number of cells may be changed to cells capable of storing n-bit information.Type: ApplicationFiled: February 23, 2017Publication date: July 4, 2019Applicant: HITACHI, LTD.Inventors: Yoshihiko FUJII, Shigeo HOMMA, Junji OGAWA, Yoshinori OHIRA
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Publication number: 20190196962Abstract: This storage system has one or more non-volatile memory devices and a processor unit that comprises one or more processors connected to the one or more non-volatile memory devices. At least a portion of the non-volatile memory of each of the one or more non-volatile memory devices comprises a user area, which is a storage area to which data is written, and an update area, which is a storage area to which update data for the original data is written. The processor unit changes the user capacity, namely the capacity of the user area, of each of the one or more non-volatile memory devices on the basis of at least one of one or more resource usage rates of the one or more non-volatile memory devices.Type: ApplicationFiled: February 20, 2017Publication date: June 27, 2019Applicant: HITACHI, LTD.Inventors: Naoya MACHIDA, Shigeo HOMMA
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Patent number: 10204003Abstract: A failure region is specified when a failure occurs in a non-volatile semiconductor memory. When a device controller reads data stored in a specific page in a plurality of non-volatile semiconductor memories to detect an uncorrectable error (UE) of the data stored in the specific page, the device controller executes a diagnosis process including specifying a specific storage circuit that is a storage circuit including the specific page, reading data stored in a part of blocks of the specific storage circuit, and specifying, on the basis of a result of reading data stored in the block, a failure region in the specific storage circuit.Type: GrantFiled: August 27, 2014Date of Patent: February 12, 2019Assignee: Hitachi, Ltd.Inventors: Kenta Ninose, Takuji Itou, Fumio Yoshioka, Takashi Tsunehiro, Go Uehara, Shigeo Homma
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Publication number: 20180275894Abstract: According to one aspect of the present invention, the storage system has a storage controller and a plurality of storage devices. Each storage device calculates its degradation level based on an error bit count (number of correctable errors that have occurred during read), and transmits the same to the storage controller. By calculating the life of each RAID group based on the received degradation levels of the respective storage devices, the storage controller specifies the RAID group predicted to reach its life before achieving a target service life (target life), and migrates the data stored in the specified RAID group to a different RAID group.Type: ApplicationFiled: January 20, 2015Publication date: September 27, 2018Inventors: Yukihiro YOSHINO, Shigeo HOMMA, Kenta NINOSE
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Publication number: 20180203631Abstract: A storage system according to one aspect of the present invention includes a plurality of storage devices using flash memory as a storage medium. The flash memory used for the storage device may include flash memory configured to operate each cell as a cell capable of storing n-bit information or a cell capable of storing m-bit information (where n<m). The storage system may periodically acquire a number of remaining erasures form the storage device and predict the lifetime of the storage device by using the acquired number of remaining erasures and the storage device operation time. If the predicted lifetime is greater than a predetermined value (service life) a predetermined number of cells may be changed to cells capable of storing m-bit information.Type: ApplicationFiled: November 27, 2015Publication date: July 19, 2018Applicant: HITACHI, LTD.Inventors: Tomotaro DOI, Shigeo HOMMA, Kenta NINOSE
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Patent number: 10013322Abstract: A storage controller stores, for each of a plurality of storage devices, a usable capacity, which is a capacity usable by the storage controller in a logical storage area, configures a first RAID group using a first storage device group among the plurality of storage devices, and allocates, on the basis of a request from a host computer, one of a plurality of pages of the logical storage area in the first RAID group to a virtual volume. The storage controller reduces, when receiving first failure information indicating a failure in a first storage device in the first storage device group from the first storage device, a usable capacity of the first storage device on the basis of the first failure information.Type: GrantFiled: June 3, 2013Date of Patent: July 3, 2018Assignee: Hitachi, Ltd.Inventors: Go Uehara, Shigeo Homma, Koji Sonoda