Abstract: A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied.

Abstract: A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied.

Abstract: The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node.

Abstract: The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node.

Abstract: The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node.

Abstract: The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node.

Abstract: A dummy bit line is provided between a pair of bit lines. The pair of bit lines is set at a power supply voltage and the dummy bit line is set at a ground voltage, and then the pair of bit lines and the dummy bit line are equalized. When a word line is activated in subsequent read operation, the pair of bit lines is at an intermediate potential lower than the power supply voltage, so that an apparent current drive capability of an access transistor decreases, and the static noise margin of a memory cell increases.

Abstract: A semiconductor memory of the present invention comprises: a static-type memory cell constituted of a pair of access transistors formed with NMOS transistors, a pair of drive transistors formed with NMOS transistors, and a pair of load transistors formed with PMOS transistors. Further, it comprises a substrate bias control unit which applies bias for increasing access speed to a substrate of any of the transistors when making access to the memory cell through adjusting electric current flown to a memory storage node in a common junction point of the three types of transistors. A substrate potential which is appropriate for reading-out, writing, memory-storing operation and low leak is applied.

Abstract: A dummy bit line is provided between a pair of bit lines. The pair of bit lines is set at a power supply voltage and the dummy bit line is set at a ground voltage, and then the pair of bit lines and the dummy bit line are equalized. When a word line is activated in subsequent read operation, the pair of bit lines is at an intermediate potential lower than the power supply voltage, so that an apparent current drive capability of an access transistor decreases, and the static noise margin of a memory cell increases.