Patents by Inventor Shigeo Koide
Shigeo Koide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8265087Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.Type: GrantFiled: October 26, 2007Date of Patent: September 11, 2012Assignees: Fujitsu Ten Limited, Fujitsu Semiconductor Limited, Renesas Electronics CorporationInventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
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Patent number: 8122316Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.Type: GrantFiled: October 25, 2007Date of Patent: February 21, 2012Assignees: Fujitsu Ten Limited, Fujitsu Semiconductor Limited, Renesas Electronics CorporationInventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
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Patent number: 8027352Abstract: A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.Type: GrantFiled: October 25, 2007Date of Patent: September 27, 2011Assignees: Fujitsu Semiconductor Limited, Renesas Technology CorporationInventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
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Publication number: 20080141074Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.Type: ApplicationFiled: October 25, 2007Publication date: June 12, 2008Applicants: FUJITSU TEN LIMITED, FUJITSU LIMITED, RENESAS TECHNOLOGY CORP.Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
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Publication number: 20080101393Abstract: A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.Type: ApplicationFiled: October 25, 2007Publication date: May 1, 2008Applicants: FUJITSU TEN LIMITED, FUJITSU LIMITED, RENESAS TECHNOLOGY CORP.Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
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Publication number: 20080101394Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.Type: ApplicationFiled: October 26, 2007Publication date: May 1, 2008Applicants: FUJITSU TEN LIMITED, FUJITSU LIMITED, RENESAS TECHNOLOGY CORPORATIONInventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
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Patent number: 6026498Abstract: A clock signal generator circuit has a clock generator for generating clock signals to be supplied to a central processing unit and to functional blocks, and clock selectors. The clock generator divides the frequency of a source clock signal, to form a clock signal having an optional period. Namely, the clock generator suppresses at least one active or inactive state of the source clock signal, to generate a clock signal whose period is an integer multiple of that of the source clock signal. The clock selectors receive the clock signals generated by the clock generator and selectively supply them to the CPU and functional blocks. The clock signal generator circuit is capable of operating a microcontroller system at a required minimum speed, to optimize the power consumption of the system.Type: GrantFiled: May 24, 1995Date of Patent: February 15, 2000Assignee: Fujitsu LimitedInventors: Takeshi Fuse, Toshiyuki Igarashi, Masaaki Tani, Atsushi Fujita, Osamu Tago, Shigeo Koide, Takashi Sugimoto
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Patent number: 4352178Abstract: A cartridge equalizer for obtaining excellent sound quality following the original sound with high fidelity by minimizing the positional shift of the cantilever fulcrum of a cartridge by mounting the cartridge equalizer to a portion near the cartridge of the tone arm of a record player and providing a well-balanced, suitable amount of weight. The cartridge equalizer includes a ring-shaped crossing rod made of a light alloy or the like having respective counterweights mounted at each end of the crossing rod, and a ring-shaped fitting positioned at the central portion of the crossing rod for fastening the cartridge equalizer to the tone arm.Type: GrantFiled: May 14, 1980Date of Patent: September 28, 1982Assignee: Masaki KitamuraInventors: Masaki Kitamura, Naoki Saisu, Shigeo Koide