Abstract: By executing the steps of sequentially retrieving buffers on a clock tree from a clock source to input pins of the cells other than the buffers and recognizing the buffer retrieved, organizing a group of the buffers recognized on the clock tree into an instance as a hierarchical block and extracting the hierarchical block as a net list, the part constituting the buffers on the clock tree once designed is organized in the hierarchical block and the hierarchical block are saved as the net list as well as the physical arrangement information of an individual buffer. After the circuit modification or net list change have been made, the hierarchical block previously saved is inserted into the net list, and the hierarchical levels are developed after automated arrangement to reproduce the physic arrangement information of the clock tree.

Abstract: In a layout design, there are executed a step 201 of defining a permitted connecting relationship of an interface signal to be transmitted across different power supplies, a step 202 of extracting the interface signal between the different power supplies based on information about each of the power regions and information about a cell connection and optimizing a circuit in such a manner that the connecting relationship of the interface signal between the different power supplies is set to be one-to-one, a logic cell arranging step 203, a step 204 of verifying whether a logic cell of the interface signal between the different power supplies is arranged in a correct power region or not, an arrangement synthesizing step 205, a step 206 of confirming a timing and a slew before wiring, an arrangement correcting step 207, and a wiring step 208. Consequently, it is possible to carry out the verification between the different power supplies in consideration of physical information as well as logic information.

Abstract: By executing the steps of sequentially retrieving buffers on a clock tree from a clock source to input pins of the cells other than the buffers and recognizing the buffer retrieved, organizing a group of the buffers recognized on the clock tree into an instance as a hierarchical block and extracting the hierarchical block as a net list, the part constituting the buffers on the clock tree once designed is organized in the hierarchical block and the hierarchical block are saved as the net list as well as the physical arrangement information of an individual buffer. After the circuit modification or net list change have been made, the hierarchical block previously saved is inserted into the net list, and the hierarchical levels are developed after automated arrangement to reproduce the physic arrangement information of the clock tree.