Abstract: An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

Abstract: A data processor being provided with a microdecoder which decodes instruction codes comprising two operation code parts, a source operand specifying part and a destination operand specifying part, wherein an optional bit area of source data (a register of a general register file or a memory) is inserted in an optional bit area (determined by the value of the first operation code part) of a destination register according to the decoding result, and an optional bit area (determined by the value of the second operation code part) of a source register is extracted and stored in an optional bit area of destination (a register of the general register file or the memory), thereby making it possible to "process the insertion and extraction operations to and from optional byte positions of registers" at a high speed with short instruction code size.

Abstract: To speed up data transfer of a plurality of registers between register banks in a microcomptuer having a register file formed by a built-in RAM and consisting of a plurality of register banks, the memory cells of the same type of registers belonging to different register banks are connected to the same bit lines. For data transfer of a plurality of registers between register banks, the word line 12 connecting a source register bank is first activated to output data to bit lines 13, and then the word line 12 connecting to a destination register bank is activated to read the data outputted to the bit lines 13, thus making it possible to speed up data transfer of a plurality of registers without the use of the internal data bus 3 of the microcomputer.

Abstract: To speed up switch between the use of a data bus by CPU for reading and writing data and the use of the data bus for refreshing a DRAM in a microcomputer having a DRAM refresh function, a terminal count signal 20 which is activated by a refresh timer 9 when a memory subsystem 8 composed of an external DRAM needs to be refreshed is directly input into a microinstruction sequencer 15 for controlling the order of executing a set of microinstructions of CPU 2. Therefore, CPU 2 can interrupt the execution of a set of microinstructions to execute a refresh cycle and can resume the execution of the interrupted set of microinstructions as controlled by the microinstruction sequencer 15 after the refresh cycle is finished.

Abstract: A data cache, for use in a memory having an address space including tag addresses for identifying blocks of storage locations and a set of select addresses for identifying storage locations in a block, includes a set select decoder that decodes only a subset of said set of select addresses that identify sub-blocks of storage locations located at the upper and lower boundaries of a block. Thus, data in storage locations accessed by addresses near block boundaries which have a high number of bit transitions is registered to the cache so that the high number of bit transitions does not have to be driven on an external bus so that noise is reduced.

Abstract: A microcomputer provided with improved interrupt handling. The frequency of a clock signal supplied to the central processing unit is increased to shorten the interrupt holding time when relatively many interrupts are occurring. When few interrupts are occurring, the frequency of the clock signal is decreased thereby reducing power consumption. The invention includes a holding factors register for storing the number of interrupt factors being held by an interrupt controller and an interrupt nesting counter for storing the number of nested interrupts in the central processing unit. The numbers stored in the holding factors register and interrupt nesting counter are compared to preset numbers. A clock control circuit changes the frequency of the system clock signal in accordance with the comparison result thereby changing the frequency of the clock signal depending on the number of occurrences of interrupts.

Abstract: In order to reduce the capacity of a character ROM without reducing the character information, n-bit bit pattern data and sequence data having information necessary for composing n-bit m components are stored in first memory means (character ROM). Second memory means has addresses corresponding to each display position on the screen and holds addresses for the first memory means as a data. In accordance with the address from the second memory means and the sequence data from the first memory means, address modifying means produces an address of a scanning line with respect to pertinent character for the first memory means. According to this address, the bit pattern data is read out from the first memory means.

Abstract: Data is transferred directly from a source register in a register file connected to a data bus from a destination register in the register file, through a read data latch, a data bus bypass mechanism, and a write data latch. Since the data bus is bypassed, the update of a data pointer is possible concurrently with the transfer of data between the source register and the destination register.

Abstract: A counter control method according to the present invention comprising the steps of:(a) allocating switching information corresponding to counters in need of being simultaneously started among switching information each serving to drive a plurality of switching means, to an address (c) of memory means to which operation control means is accessible at a time, and(b) driving said switching means using said switching information so allocated to thereby start said plurality of the counters.

Abstract: A semiconductor read-only memory device includes first and second MOS field effect mode transistors (MOSFET) as memory elements storing either one of binary values of binary information. The first MOSFET has such a relatively long effective gate length that it becomes conductive upon receipt of a first relatively high gate voltage applied thereto as a memory selection signal and becomes non-conductive upon receipt of a second relatively low gate voltage. The second MOSFET, on the other hand, has such a relatively short effective gate length that it becomes conductive whether the first or second gate voltage is applied thereto.