Patents by Inventor Shigeo Ogasawara

Shigeo Ogasawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6022797
    Abstract: First through holes of a relatively small diameter and second through holes of a relatively great diameter are formed in proper shapes by separate processes, respectively, in a first layer insulating film. The second through holes are tapered toward a layer underlying the first layer insulating film. First, the first through holes are formed in the first layer insulating film, the first through holes are filled up with plug electrodes, and the second through holes are formed in the first layer insulating film. When filling up the first and the second through holes formed in the first layer insulating film with plug electrodes, a first conductive film deposited over the first layer insulating film is etched back to fill up the first through holes with the plug electrodes, and then etch back residues remaining on the side walls of the second through holes are removed.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: February 8, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Ogasawara, Shigeru Takahashi, Noriaki Oka, Tadayasu Miki, Masahito Hiroshima
  • Patent number: 5986294
    Abstract: A semiconductor integrated circuit having three or more layers of wiring is provided with a plurality of lines of bonding pads arranged along the outer peripheral portion of a semiconductor chip. The bonding pads on the inner line side and those on the outer line side are arranged in a zigzag manner. First outgoing wiring for electrically connecting the bonding pads on the inner line side and internal circuits (input/output buffer circuits) is formed in one layer of wiring or a plurality of layers of wiring including at least the uppermost layer of wiring, and second outgoing wiring for electrically connecting the bonding pads on the outer line side and the internal circuits (the input/output buffer circuits) is formed in a plurality of layers of wiring other than the layer in which the first outgoing wiring is formed.
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: November 16, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Tadayasu Miki, Shigeo Ogasawara, Noriaki Oka, Shigeru Takahashi, Mitsuaki Katagiri
  • Patent number: 5892276
    Abstract: A semiconductor integrated circuit having three or more layers of wiring is provided with a plurality of lines of bonding pads arranged along the outer peripheral portion of a semiconductor chip. The bonding pads on the inner line side and those on the outer line side are arranged in a zigzag manner. First outgoing wiring for electrically connecting the bonding pads on the inner line side and internal circuits (input/output buffer circuits) is formed in one layer of wiring or a plurality of layers of wiring including at least the uppermost layer of wiring, and second outgoing wiring for electrically connecting the bonding pads on the outer line side and the internal circuits (the input/output buffer circuits) is formed in a plurality of layers of wiring other than the layer in which the first outgoing wiring is formed.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: April 6, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Tadayasu Miki, Shigeo Ogasawara, Noriaki Oka, Shigeru Takahashi, Mitsuaki Katagiri