Abstract: Provided is a variable resistive element which performs high speed and low power consumption operation. The variable resistive element comprises a metal oxide layer between first and second electrodes wherein electrical resistance between the first and second electrodes reversibly changes in accordance with application of electrical stress across the first and second electrodes. The metal oxide layer has a filament, which is a current path where the density of a current flowing between the first and second electrodes locally increases. A portion including at least the vicinity of an interface between the certain electrode, which is one or both of the first and second electrodes, and the filament, on an interface between the certain electrode and the metal oxide layer is provided with an interface oxide which is an oxide of at least one element included in the certain electrode and different from the oxide of the metal oxide layer.

Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

Abstract: A variable resistance element comprises a variable resistor of strongly-correlated material sandwiched between two metal electrodes, and the electric resistance between the metal electrodes varies when a voltage pulse is applied between the metal electrodes. Such a switching operation as the ratio of electric resistance between low and high resistance states is high can be attained by designing the metal electrodes and variable resistor appropriately based on a definite switching operation principle. Material and composition of the first electrode and variable resistor are set such that metal insulator transition takes place on the interface of the first electrode in any one of two metal electrodes and the variable resistor by applying a voltage pulse. Two-phase coexisting phase of metal and insulator phases can be formed in the vicinity of the interface between the variable resistor and first electrode by the work function difference between the first electrode and variable resistor.

Abstract: Provided is a nonvolatile semiconductor device capable of performing writing operations of different resistance changes for memory cells having variable resistive elements whose resistive characteristics are changed by voltage applications, individually and simultaneously. The device includes: a load resistive characteristic variable circuit for each bit line connected commonly with the memory cells on the same column for selecting one of two load resistive characteristics according to a first writing operation where the resistive characteristics of the variable resistive element to be written transit from a low resistance state to a high resistance state or a second writing operation where they transit reversely; and a writing voltage pulse application circuit for applying a first voltage pulse in a first writing operation and a second voltage pulse in a second writing operation to the memory cells to be written through the load resistive characteristic variable circuits and the bit limes.

Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

Abstract: The variable resistance element of the present invention is a variable resistance element having an electrode, the other electrode, and a metal oxide material sandwiched between the electrodes and having an electrical resistance, between the electrodes, changing reversibly in response to a voltage applied between the electrodes. The variable resistance element further includes, inside the metal oxide material, a low resistance material having a lower electrical resistance than the metal oxide material and being out of contact with at least either one of the electrodes. This makes it possible to reduce a forming voltage for providing a conductive section inside the metal oxide material, without causing a leakage current to increase.

Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

Abstract: Provided is a variable resistive element which performs high speed and low power consumption operation. The variable resistive element comprises a metal oxide layer between first and second electrodes wherein electrical resistance between the first and second electrodes reversibly changes in accordance with application of electrical stress across the first and second electrodes. The metal oxide layer has a filament, which is a current path where the density of a current flowing between the first and second electrodes locally increases. A portion including at least the vicinity of an interface between the certain electrode, which is one or both of the first and second electrodes, and the filament, on an interface between the certain electrode and the metal oxide layer is provided with an interface oxide which is an oxide of at least one element included in the certain electrode and different from the oxide of the metal oxide layer.

Abstract: Provided is a nonvolatile semiconductor device capable of performing writing operations of different resistance changes for memory cells having variable resistive elements whose resistive characteristics are changed by voltage applications, individually and simultaneously. The device comprises: a load resistive characteristic variable circuit for each bit line connected commonly with the memory cells on the same column for selecting one of two load resistive characteristics according to a first writing operation where the resistive characteristics of the variable resistive element to be written transit from a low resistance state to a high resistance state or a second writing operation where they transit reversely; and a writing voltage pulse application circuit for applying a first voltage pulse in a first writing operation and a second voltage pulse in a second writing operation to the memory cells to be written through the load resistive characteristic variable circuits and the bit limes.

Abstract: A variable resistance element comprises a variable resistor of strongly-correlated material sandwiched between two metal electrodes, and the electric resistance between the metal electrodes varies when a voltage pulse is applied between the metal electrodes. Such a switching operation as the ratio of electric resistance between low and high resistance states is high can be attained by designing the metal electrodes and variable resistor appropriately based on a definite switching operation principle. Material and composition of the first electrode and variable resistor are set such that metal insulator transition takes place on the interface of the first electrode in any one of two metal electrodes and the variable resistor by applying a voltage pulse. Two-phase coexisting phase of metal and insulator phases can be formed in the vicinity of the interface between the variable resistor and first electrode by the work function difference between the first electrode and variable resistor.

Abstract: The variable resistance element of the present invention is a variable resistance element having an electrode, the other electrode, and a metal oxide material sandwiched between the electrodes and having an electrical resistance, between the electrodes, changing reversibly in response to a voltage applied between the electrodes. The variable resistance element further includes, inside the metal oxide material, a low resistance material having a lower electrical resistance than the metal oxide material and being out of contact with at least either one of the electrodes. This makes it possible to reduce a forming voltage for providing a conductive section inside the metal oxide material, without causing a leakage current to increase.

Abstract: The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower electrode lines and insulating layers provided on both sides of the lower electrode line so as to be substantially uniform in the height thus for patterning the lower electrode lines, a memory element layer depositing step of depositing on the lower electrode lines a memory element layer for the memory elements, and an annealing step of annealing with heat treatment either between the lower electrode lines forming step and the memory element layer depositing step or after the memory element layer depositing step so that any damages caused by the polishing of the surface of the lower electrode lines can be eliminated.

Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

Abstract: The present invention provides a large transport ship in which the shape of a ship bottom 1a from a bow 1h to a stern 1t, when viewed on a cross-section perpendicular to the longitudinal direction of the ship bottom 1a, is tapered towards the center CL of the ship bottom in the widthwise direction. Consequently, it is possible to resolve problems associated with changes in the draft corresponding to the state of the load, without using ballast water.

Abstract: The present invention provides a large transport ship in which the shape of a ship bottom 1a from a bow 1h to a stern 1t, when viewed on a cross-section perpendicular to the longitudinal direction of the ship bottom 1a, is tapered towards the center CL of the ship bottom in the widthwise direction. Consequently, it is possible to resolve problems associated with changes in the draft corresponding to the state of the load, without using ballast water.

Abstract: There is provided a semiconductor memory device with extremely less deterioration of characteristics of dielectric thin film and with high stability. A TaSiN barrier metal layer 13 is formed on a Pt upper electrode 12. This TaSiN barrier metal layer 13 has electrical conductivity and hydrogen-gas blocking property and besides has an amorphous structure stable in high temperature region without crystallizing even during firing for crystallization of an oxide ferroelectric thin film (SBT thin film) 11. Then, hydrogen gas generated during later formation of a second interlayer insulating film 15 is reliably blocked from invading into the oxide ferroelectric thin film 11, by which characteristic deterioration of the oxide ferroelectric thin film 11 due to hydrogen gas is prevented.

Abstract: A method of forming a device isolation region includes the steps of: forming a first dielectric film and an oxidation-resistant deposition film successively on a semiconductor substrate; forming a trench groove in the semiconductor substrate by successively processing the oxidation-resistant deposition film, the first dielectric film and the semiconductor substrate by anisotropic etching; forming a second dielectric film to cover at least an inner surface of the trench groove; depositing a third dielectric film in the trench groove so that the thickness of the third dielectric film buried in the trench groove is larger than a depth of the trench groove; planarizing a surface of the third dielectric film and an upper surface of the trench groove; and removing the oxidation-resistant deposition film and the first dielectric film to form the device isolation region, wherein a thermal treatment of the entire substrate is carried out to densify the third dielectric film and to oxidize an interface between the seco

Abstract: A method of fabricating a semiconductor memory device comprises the steps of: (a) forming an interlayer insulating film on a semiconductor substrate, opening a contact hole in said interlayer insulating film, and burying a plug in said contact hole; (b) forming a first insulating film on said interlayer insulating film inclusive of said plug, and forming a trench in said first insulating film above said plug; (c) forming a first conductive film on said first insulating film inclusive of said trench, and etching back said first conductive film by a chemical mechanical polishing method to form a bottom electrode inside said trench; (d) forming a high dielectric film or a ferroelectric film and a second conductive film in this order on said first insulating film inclusive of said bottom electrode; and (e) patterning simultaneously said high dielectric film or ferroelectric film and said second conductive film to form a capacitor insulating film and a top electrode.

Abstract: A process for producing a semiconductor device including the steps of:(a) forming a trench in a semiconductor substrate at a portion thereof where an isolating zone is to be formed,(b) doping the substrate with an impurity element from the inner wall thereof defining the trench to form a high-concentration impurity diffused region, and(c) etching the bottom surface of the trench to increase the depth of the trench, thereby separating the impurity diffused region to form the isolating zone,which is useful for the fabrication of semiconductor devices of high integration with low well resistance.