Abstract: An image processing apparatus includes a memory having a first region and a second region. The first memory region holds original image data. A first calculation device calculates addresses of segments of the first memory region. A second calculation device calculates addresses of segments of the second memory region. The original image data are transferred from the first memory region to the second memory region in accordance with the calculated addresses of the segments of the first and second memory regions. The first calculation device and the second calculation device are mutually independent. The calculation of the addresses of the segments of the first memory region is performed simultaneously with the calculation of the addresses of the segments of the second memory region.

Abstract: An apparatus for expanding or contracting image data includes an input for storing the image data to be processed, a first barrel shifter for shifting the output data of the input register, a control register for storing a mapping pattern which indicates a position of the image data bits to be extracted in the expansion mode or which indicates the number of times when the image data are to be copied, an expansion and contraction circuit for expanding or contracting the image data by referring to the mapping pattern, and a second barrel register for shifting the output image data of the expansion and contraction circuit before the data are loaded in an output data register.

Abstract: Image data is transposed between successively arranged first data points in a first image field and successively arranged second data points in a second image field by a method comprising: (1) successively specifying a first data point (i); (2) summing first control data indicative of a residue with second control data indicative of a constant value; (3.sub.1) if the result of the summation does not exceed a predetermined value, updating the first control data with the summation result and specifying a second data point (j) corresponding to the specified first data point, or (3.sub.

Abstract: A central processing unit of a computer system comprises a programmable logic array which is constructed of an AND matrix and an OR matrix. The AND matrix is responsive to a machine language instruction and to a number of a region for selecting one row from a plurality of rows arranged in the AND matrix. The OR matrix, which also has a plurality of rows, is responsive to the selected row for selecting one row therefrom. In each of the rows of the OR matrix a microaddress and a number of a region to be used for producing a subsequent microaddress are prewritten so that information on a microaddress and information on a region number are respectively obtained. At least one microinstruction included in a microprogram will be read out from a read-only memory in accordance with the obtained microaddress to execute the same, while a microaddress of a subsequent microprogram is produced in the programmable logic array.