Abstract: An information processing device includes: a distribution management unit that performs instruction processing pertaining to image distribution for image data captured at a specific event and transmitted to a server device; an event data management unit that performs processing for managing, in association with the image data, evaluation information for an image that is distributed; and a filter processing unit that performs filtering processing on the image data using the evaluation information as a filter condition.

Abstract: An information processing device performs a control process that provides a user interface that allows a designation operation for designating an extraction condition for an image group of images captured at an event related tom marriage, and an extraction process that extracts an image from the image group according to the designated extraction condition.

Abstract: There is provided an information processing method characterized in that, in accordance with an instruction from a host CPU 411, either a CPU 103 or 104 loads a common code and an instruction code defined to be executed by itself from an external memory 110 into an internal memory 101, the other CPU loads an instruction code defined to be executed by itself from the external memory 110 into the internal memory 101, and then the respective CPUs load the respective instruction codes defined to be executed by themselves that are loaded in the internal memory 101, and execute the common code that is loaded in the internal memory 101 as required.

Abstract: There is provided an information processing method characterized in that, in accordance with an instruction from a host CPU 411, either CPU 103 or 104 loads a common code and an instruction code defined to be executed by itself from an external memory 110 into an internal memory 101, the other CPU loads an instruction code defined to be executed by itself from the external memory 110 into the internal memory 101, then the respective CPUs load the respective instruction codes defined to be executed by themselves that are loaded in the internal memory 101, and executing the common code that is loaded in the internal memory 101 as required.