Patents by Inventor Shigeo Tani
Shigeo Tani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9277299Abstract: A line switching device includes multiple input ports to which signals are input and that include first input ports and second input ports different from the first input ports; multiple output ports that include given output ports; a branch unit that branches first signals input from the first input ports; and a switch that selectively outputs, among second signals input from the second input ports and branched signals branched from the first signals by the branch unit, signals that are to be switched to an output port among the given ports.Type: GrantFiled: August 10, 2012Date of Patent: March 1, 2016Assignee: FUJITSU LIMITEDInventors: Shigeo Tani, Takashi Umegaki
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Patent number: 9253553Abstract: A transmission apparatus includes: an assigning unit to assign a number to a group of concatenation information of leading and dependent data which are multicast or broadcast; a retrieval unit to retrieve the concatenation information of the leading data corresponding to the dependent data, the leading and dependent data having the same number; a regeneration unit to regenerate concatenation information of the dependent data in accordance with the concatenation information of the leading data; a storage unit to store switch information of the leading data, the switch information representing a switch which switches output destinations of the leading and dependent data; an information retrieval unit to refer to the storage unit in accordance with leading data information included in the concatenation information of the dependent data so as to retrieve switch information of the dependent data; and a switching unit to switch the output destination of the dependent data.Type: GrantFiled: December 14, 2012Date of Patent: February 2, 2016Assignee: FUJITSU LIMITEDInventors: Shigeo Tani, Takashi Umegaki
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Patent number: 8582597Abstract: There is provided a time slot interchanger for processing channel setting data functioning as control data for interchanging time slots of multiplexed transmission data. In the time slot interchanger, processing of the channel setting data based on alarm data is performed in accordance with a preset first transmission capacity, and with respect to the channel setting data in accordance with a preset second transmission capacity, processing of the channel setting data in accordance with the first transmission capacity is dispersedly performed in a time series manner.Type: GrantFiled: June 3, 2008Date of Patent: November 12, 2013Assignee: Fujitsu LimitedInventors: Mitsuhiro Kawaguchi, Shosaku Yamasaki, Shigeo Tani, Hideki Matsui
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Patent number: 8564355Abstract: There is provided a clock device including: a clock circuit to generate a plurality of clock signals, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part.Type: GrantFiled: January 11, 2011Date of Patent: October 22, 2013Assignee: Fujitsu LimitedInventors: Shigeo Tani, Takashi Umegaki
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Publication number: 20130094805Abstract: A line switching device includes multiple input ports to which signals are input and that include first input ports and second input ports different from the first input ports; multiple output ports that include given output ports; a branch unit that branches first signals input from the first input ports; and a switch that selectively outputs, among second signals input from the second input ports and branched signals branched from the first signals by the branch unit, signals that are to be switched to an output port among the given ports.Type: ApplicationFiled: August 10, 2012Publication date: April 18, 2013Applicant: FUJITSU LIMITEDInventors: Shigeo TANI, Takashi Umegaki
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Patent number: 8355632Abstract: In a transmission apparatus, unlike in the conventional transmission apparatus, a protection switch is not arranged on the signal path, but a TSI having only the basic function performs the function of the protection switch as a substitute, a processing unit to perform the switching function at a low rate is artificially constructed on a TSI, the switch process of SONET protection type is artificially executed by the TSI, and a signal for controlling the TSI function is further controlled thereby to realize the protection switch function. The logic of switching at the main signal rate in addition to the conventional TSI function is deleted.Type: GrantFiled: January 21, 2010Date of Patent: January 15, 2013Assignee: Fujitsu LimitedInventors: Mitsuhiro Kawaguchi, Shosaku Yamasaki, Shigeo Tani, Hideki Matsui
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Patent number: 8355318Abstract: There is provided a node apparatus having a plurality of interface units for interfacing to a transmission line, switch units of a work system and a protection system for switching signals of the transmission line, and a service selector used to relieve a network failure over ring networks interconnected by node apparatuses, the node apparatus including a first controller for controlling the service selector in the switch units, and a second controller for controlling setting information of alarm detection in case of using the service selector in the interface units.Type: GrantFiled: October 29, 2009Date of Patent: January 15, 2013Assignee: Fujitsu LimitedInventors: Mitsuhiro Kawaguchi, Shigeo Tani, Ryoji Azumi, Hideki Matsui
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Patent number: 8295161Abstract: A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.Type: GrantFiled: December 16, 2009Date of Patent: October 23, 2012Assignee: Fujitsu LimitedInventors: Ryoji Azumi, Takashi Umegaki, Shigeo Tani, Shosaku Yamasaki
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Publication number: 20110175653Abstract: There is provided a clock device including: a clock circuit to generate a plurality of clock signals, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part.Type: ApplicationFiled: January 11, 2011Publication date: July 21, 2011Applicant: FUJITSU LIMITEDInventors: SHIGEO TANI, TAKASHI UMEGAKI
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Publication number: 20110170864Abstract: An interface device for demultiplexing, from a first frame in a transport network, a plurality of second frames multiplexed into the first frame is provided. The interface device includes an extractor configured to extract a plurality of data groups to constitute the first frame, and a second frame generator configured to create the second frames based on the plurality of data groups extracted by the extractor.Type: ApplicationFiled: January 10, 2011Publication date: July 14, 2011Applicant: FUJITSU LIMITEDInventors: Shigeo TANI, Hidenori Kiuchi, Takashi Umegaki, Ryoji Azumi, Shigehisa Sakahara
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Publication number: 20100158514Abstract: A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.Type: ApplicationFiled: December 16, 2009Publication date: June 24, 2010Applicant: FUJITSU LIMITEDInventors: Ryoji AZUMI, Takashi Umegaki, Shigeo Tani, Shosaku Yamasaki
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Publication number: 20100124416Abstract: In a transmission apparatus, unlike in the conventional transmission apparatus, a protection switch is not arranged on the signal path, but a TSI having only the basic function performs the function of the protection switch as a substitute, a processing unit to perform the switching function at a low rate is artificially constructed on a TSI, the switch process of SONET protection type is artificially executed by the TSI, and a signal for controlling the TSI function is further controlled thereby to realize the protection switch function. The logic of switching at the main signal rate in addition to the conventional TSI function is deleted.Type: ApplicationFiled: January 21, 2010Publication date: May 20, 2010Applicant: FUJITSU LIMITEDInventors: Mitsuhiro Kawaguchi, Shosaku Yamasaki, Shigeo Tani, Hideki Matsui
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Publication number: 20100124417Abstract: There is provided a node apparatus having a plurality of interface units for interfacing to a transmission line, switch units of a work system and a protection system for switching signals of the transmission line, and a service selector used to relieve a network failure over ring networks interconnected by node apparatuses, the node apparatus including a first controller for controlling the service selector in the switch units, and a second controller for controlling setting information of alarm detection in case of using the service selector in the interface units.Type: ApplicationFiled: October 29, 2009Publication date: May 20, 2010Applicant: FUJITSU LIMITEDInventors: Mitsuhiro KAWAGUCHI, Shigeo TANI, Ryoji AZUMI, Hideki MATSUI
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Publication number: 20080304508Abstract: There is provided a time slot interchanger for processing channel setting data functioning as control data for interchanging time slots of multiplexed transmission data. In the time slot interchanger, processing of the channel setting data based on alarm data is performed in accordance with a preset first transmission capacity, and with respect to the channel setting data in accordance with a preset second transmission capacity, processing of the channel setting data in accordance with the first transmission capacity is dispersedly performed in a time series manner.Type: ApplicationFiled: June 3, 2008Publication date: December 11, 2008Applicant: FUJITSU LIMITEDInventors: Mitsuhiro Kawaguchi, Shosaku Yamasaki, Shigeo Tani, Hideki Matsui
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Patent number: 6977889Abstract: There is described a cross-connect apparatus which can apply a cross-connect operation in place of a function of a hard switch that has conventionally been used for a purpose other than a cross-connect operation, by selection of line setting information used for path switching and service selection operations, and by performing a cross-connect operation based on the information, thereby preventing redundant configuration of the cross-connect apparatus and diminishing power consumption.Type: GrantFiled: September 1, 1999Date of Patent: December 20, 2005Assignee: Fujitsu LimitedInventors: Mitsuhiro Kawaguchi, Shigeo Tani
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Publication number: 20040213246Abstract: The invention provides an improved ATM technique which can achieve common processing without depending upon the level or the mode of a cell used by the physical layer side, the bit width in the same mode, the parity adding method depending upon the level or the operation mode and the ATM layer side can cope individually with all modes where all cell information such as a level, a mode, presence or absence of a UDF, a bit width and a parity adding method is recognized in advance. An ATM communication apparatus includes a physical layer side interface apparatus which in turn includes a FIFO processing section and a UTOPIA interface section, and an ATM layer side interface apparatus which in turn includes a detection circuit, a UTOPIA circuit, and a selector.Type: ApplicationFiled: February 27, 2001Publication date: October 28, 2004Inventors: Shigeo Tani, Yasuo Miyawaki, Hiroki Kondo
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Patent number: 6587527Abstract: A frame synchronism processing apparatus including a first detecting unit for detecting the synchronism of a subframe, a second detecting unit for detecting the synchronism of a multiframe, and a synchronism detection retrying control unit for forcibly bringing the first detecting unit and the second detecting unit into a synchronism detection retrying mode if the second detecting unit has failed to detect the synchronism of the multiframe. Assuring that a false synchronous state is brought about on the subframe synchronism with the result that the detection of the synchronism of the multiframe has been failed, the detection of synchronism of the subframes and the detection of synchronism of the multiframe are retried, thus avoiding a deadlock of frame synchronism process due to the possible false synchronous state and hence improving the reliability in synchronism process.Type: GrantFiled: August 25, 1999Date of Patent: July 1, 2003Assignee: Fujitsu LimitedInventors: Shigeo Tani, Toshinori Koyanagi
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Publication number: 20020098265Abstract: A method of processing starch grain material for use in a fermenting process subsequently thereto is disclosed. Prior to subjecting the material to the fermenting step, the material is subjected to a microwave irradiating step and this microwave irradiating step is effected on the starch grain material which is in a dry condition storable at a room temperature with simultaneous application of hot air current thereto. A method of manufacturing a fermented product using the material processed by the method above is also disclosed.Type: ApplicationFiled: October 19, 2001Publication date: July 25, 2002Applicant: KONISHI FERMENTATION RESEARCH LAB. PTY., LTD.Inventors: Yasuo Konishi, Shigeo Tani, Masaaki Uozumi, Takeharu Miyamoto
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Patent number: 5619532Abstract: A digital communication system includes a first station, a second station and a network therebetween. The first station includes a clock selecting device for selecting one clock from a plurality of different clocks; and a transmitting device for transmitting frames to the second station based on the selected clock. The second station includes an evaluating device for evaluating transmission quality of data in each of the frames received from the first station; and a quality message inserting device for inserting the evaluated transmission quality as a quality message into a part of the corresponding frame to be transmitted to the first station.Type: GrantFiled: June 7, 1995Date of Patent: April 8, 1997Assignee: Fujitsu LimitedInventors: Shigeo Tani, Katsuaki Yamanaka, Hironori Aono, Toshiaki Kinoshita