Abstract: In a computer system having a double PCI bus configuration, an inter-bus control circuit for relaying a first PCI bus and a second PCI bus is provided with a memory control mechanism common to devices connected to the second PCI bus and an interrupt control mechanism for controlling interrupts between local processors, in addition to a control function for controlling the buses. The inter-bus control circuit having the above mechanisms can be implemented by a single-chip integrated circuit. The integrated inter-bus control circuit prevents the use of a plurality of identical decoder circuits, an increase in the number of parts, and an increase in mounting area, thus providing a compact and low price computer system.

Abstract: In a client server system including a server machine including a network device and a plurality of client machines each including a network machine, the server machine includes a unit to send shutdown information indicating the shutdown state thereof and restoration information to the client machines and each client machine includes a control logic operative at reception of shutdown information from the server machine to conduct an attempt for line connection to the server machine at a desired interval of time. As a result, at restoration of the server machine from the shutdown state, the state of connection to each client machine is automatically achieved from the client side. Accordingly, at shut-down of the server machine, the logical line connection can be reconstructed without any intervention of the user of each client machine.

Abstract: A virtual machine for operating, on a base machine, applications software for a target machine. The virtual machine includes first display control hardware for the base machine, second display control hardware for the target machine, a virtual machine monitor for emulating the operation of the target machine by utilizing the second display control hardware for displaying operation, and a selector for selecting one of the first display control hardware and the second display control hardware depending on whether the virtual machine monitor is operable in a target machine mode or a base machine mode. The OS of the base machine is utilized for the virtual machine without modification.

Abstract: A plurality of process requests generated from processing units, for example, direct memory access (DMA) channels are controlled by a preference circuit in accordance with a priority level assigned to each of the processing unit. An information of the highest priority obtained processing unit and its priority level is stored in latches. Another process requests having the same priority level as the stored processing unit are inhibited from being supplied to the preference circuit, so that the first generated process request is accepted and executed prior to acceptance of the another process requests having the same priority level.

Abstract: A data transfer control apparatus for a co-processor system. The co-processor system includes a memory; a memory bus connected to the memory; a main processor connected to the memory bus and having a control circuit for controlling data read/write relative to the memory, the main processor performing data transfer from/to the memory bus via a first data input/output terminal; and a co-processor connected to the memory bus via a second data input/output terminal. The control apparatus includes a high impedance setting circuit for selectively setting the first data input/output terminal at a high impedance state to electrically isolate the first data input/output terminal from the memory bus; and a control signal generator for selectively outputting a control signal to the high impedance setting circuit to cause the high impedance setting circuit to set the first data input/output terminal at the high impedance state.

Abstract: A bus master and a plurality of bus slaves are connected through a data bus and a control bus, and data transfer of hand shake system is performed. In the control bus, at least data strobe signal from the bus master to the bus slave and data confirmation signal from the bus slave to the bus master are transmitted. The data strobe signal from the bus master is one inputted to a bus strobe control circuit. The data confirmation signal from the bus slave is also inputted to the bus strobe control circuit, and the control circuit supervises level of the data confirmation signal being asserted and confirms negation, and then asserts the data strobe signal to the bus slave. Thereafter, a next data transfer is started.

Abstract: A detector for detecting the radiation state of a display surface is disposed in a cathode ray tube in order to improve the color reproducibility of a color display. Revise order signals as standard signals are applied to obtain a difference signal between the radiation quantity of a color signal that must be displayed originally and the output signal of the detector, and a circuit for compensating for the radiation order signal is disposed in a path through which the radiation order signal is applied to the cathode ray tube.

Abstract: An apparatus for shading a polyhedron at high speed is disclosed which includes the combination of a polygon-scan line conversion processor and an inner product interpolation processor for obtaining a pair of inner products of vectors indicative of a relation among the direction of a normal, the direction of a light source and the direction of a view point each viewed at a point within a polygon having a plurality of vertices, on the basis of the position of said point in the polygon and the direction of a normal at each of the vertices, a table searched on the basis of the inner products of vectors and holding a series of brightness data which have previously been calculated for a series of values of each of the inner products of vectors, a buffer for storing the result of table search for the above table, and a D/A conversion circuit for converting the result of table search into a signal which is used as a brightness control signal in a display device.

Abstract: A graphic processor is provided with a buffer corresponding to one of a plurality of display blocks forming a display face, and a refresh memory connected to the buffer. The buffer stores therein only position information of dots which are included in one display block and are a portion of dots forming a pattern. In the refresh memory, dots are stored in a memory region corresponding to the display block at positions indicated by the above position information, in accordance with color data supplied independently of the position information. This processing is performed for all of display blocks where the pattern is present, to write pattern data in the refresh memory. Thus, it is not required to provide buffers, the number of which is equal to the number of colors used for displaying the pattern in colors, but the number of buffers can be reduced.

Abstract: An apparatus for filling an interior of a shape to be displayed on a raster scan CRT which reads out a refresh memory. The apparatus includes a memory for storing information of starting points and ending points for filling. The write of a filling color code into the refresh memory is initiated and terminates in response to the filling starting point and the filling ending point, respectively, but inhibited at its memory locations on the contour of the shape. The direction of the filling is perpendicular to the raster scanning of the CRT.

Abstract: A graphic display apparatus for generating a vector comprises registers for storing a value R of a vector discrimination, a positive increment P and a negative increment N, and flip-flops for storing magnitude information of .DELTA.X, .DELTA.Y, and .DELTA.X and .DELTA.Y. An address counter of a refresh memory is counted up or down in accordance with the contents of those flip-flops. A control circuit for updating the value R of the vector discrimination is also provided, so that the vector can be generated at a high speed. The registers and the flip-flops are constructed in two stages so that data for generating the next vector can be prepared while the current vector is generated.

Abstract: A micro program control system for use in a data processing system includes a subsidiary control memory for storing the first micro instructions of respective micro programs, and a control memory for storing the second and the remaining micro instructions of the respective micro programs. The subsidinary control memory is coupled to a main memory in which macro instructions of a program for the data processing system are stored. The operation code of the macro instruction includes a code to address the first micro instruction in the subsidiary control memory, so that one of the first micro instructions can be accessed to supply into a control register when the macro instruction is read out from the main memory to an instruction register of the data processing system, whereby control signals for controlling the operation of the data processing system are delivered from the control register according to the contents of the first micro instruction.