Patents by Inventor Shigeru Honjiyo

Shigeru Honjiyo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory with divided bit load and data bus lines
    Patent number: 5172335
    Abstract: A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified.
    Type: Grant
    Filed: July 1, 1991
    Date of Patent: December 15, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Sasaki, Osamu Minato, Shigeru Honjiyo, Koichiro Ishibashi, Toshiaki Masuhara
  • Semiconductor memory with divided bit load and data bus lines
    Patent number: 4935901
    Abstract: A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified.
    Type: Grant
    Filed: February 19, 1988
    Date of Patent: June 19, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Sasaki, Osamu Minato, Shigeru Honjiyo, Koichiro Ishibashi, Toshiaki Masuhara