Patents by Inventor Shigeru Inada

Shigeru Inada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100241932
    Abstract: An error detector/corrector includes an ECC cache unit configured to store an error bit address which represents an error location by associating the error bit address with an error page address and a coefficient ? of an error location polynomial; a comparison unit configured to check for a match by comparing new values with stored values, where the new values are an error page address detected by a syndrome calculation unit and a coefficient ? of the error location polynomial calculated by a polynomial calculation unit while the stored values are an error page address and a coefficient ? of the error location polynomial stored in the ECC cache unit; and a first error localization unit configured to identify a location of the error bit address stored in the ECC cache unit as the error location when the comparison unit determines that the compared values match.
    Type: Application
    Filed: September 10, 2009
    Publication date: September 23, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji SAKAUE, Yukio Ishikawa, Shigeru Inada
  • Patent number: 6462782
    Abstract: In a data extraction circuit used for reproducing character data such as a closed caption and a text, a horizontal sync digital PLL circuit generates an fh sync system clock signal, which is synchronized with a horizontal sync signal fh, in response to a digital video signal from an ADC. Based on the fh sync system clock signal, a clock generation circuit generates a data extracting clock signal which is synchronized with the horizontal sync signal fh. The data extracting clock signal can thus be caused to follow horizontal jitters. Consequently, character data can be reproduced with stability, irrespective of variations in frequency.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: October 8, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Honda, Shigeru Inada
  • Patent number: 4234022
    Abstract: A novel woven fabric of triple-weft weave in accordance with this invention comprises a floating first weft and a floating third weft each comprising filamentary or spun yarns consisting mainly of extra fine fibers or filaments having extra fine denier. It further comprises a second weft of heavier denier woven between said first and third wefts and a warp of relatively heavy denier.The fabric of this invention has excellent characteristics such as good crease resistance, permanent pleatability, excellent resiliency, soft touch on both front and back fabric surfaces, usefulness to an apparel without lining and reversible high quality.
    Type: Grant
    Filed: December 7, 1978
    Date of Patent: November 18, 1980
    Assignee: Toray Industries, Inc.
    Inventors: Miyoshi Okamoto, Syusuke Yoshida, Shigeru Inada